Use an enum to represent registers, parse txt files, check CPU state against expected
This commit is contained in:
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305ac557fa
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08874c4533
@ -66,7 +66,7 @@ get_op :: proc(inst: Instruction) -> (Op, bool) {
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}
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return op, interseg
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}
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parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, processed: ^int, word: bool, has_segreg: Maybe(Register)) -> Operand {
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parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, processed: ^int, word: bool, has_segreg: Maybe(RegisterId)) -> Operand {
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operand: Operand = None{}
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switch opinfo {
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case .None:
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@ -80,11 +80,11 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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case .SecondByteLast3: reg = data[1] & 0b111
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}
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if opinfo == .SegmentRegister {
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operand = (RegisterId){id = SEGMENT_REGISTER_START + (int)(reg), access = .Full}
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operand = (RegisterId){idx = SEGMENT_REGISTER_START + (int)(reg), access = .Full}
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} else if word {
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operand = RegisterId { id = (int)(reg), access = .Full }
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operand = RegisterId { idx = (int)(reg), access = .Full }
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} else {
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operand = RegisterId { id = (int)(reg % 4), access = reg < 4 ? .Low : .High }
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operand = RegisterId { idx = (int)(reg % 4), access = reg < 4 ? .Low : .High }
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}
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case .RegisterMemory:
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mod := data[1] >> 6
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@ -107,9 +107,9 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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processed^ += 2
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} else if mod == 3 {
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if word {
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op = RegisterId { id = (int)(rm), access = .Full }
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op = RegisterId { idx = (int)(rm), access = .Full }
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} else {
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op = RegisterId { id = (int)(rm % 4), access = rm < 4 ? .Low : .High }
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op = RegisterId { idx = (int)(rm % 4), access = rm < 4 ? .Low : .High }
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}
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}
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operand = op
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@ -126,7 +126,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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operand = Immediate { value = u16(data[processed^]), size = .Unsigned8 }
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processed^ += 1
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case .Accumulator:
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operand = RegisterId { id = 0, access = word ? .Full : .Low }
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operand = RegisterId { idx = 0, access = word ? .Full : .Low }
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case .DirectAddress:
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// operand = DirectAddress { value = get_i16(data[1:]) }
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operand = (DirectAddress)(get_i16(data[1:]))
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@ -136,10 +136,10 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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// NOTE: In order to mimic the label offset, you have to take the value you got and add two
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operand = (Jump)((i8)(data[1]) + 2)
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case .VariablePort:
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operand = RegisterId { id = (int)(variable_port.code), access = .Full }
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operand = RegisterId { idx = (int)(Register.dx), access = .Full }
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case .ShiftRotate:
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v_flag := data[0] & 0b10 != 0
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operand = v_flag ? RegisterId { id = 1, access = .Low } : Immediate { value = 1 }
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operand = v_flag ? RegisterId { idx = 1, access = .Low } : Immediate { value = 1 }
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case .Repeat:
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bits := (data[1] & 0b1110) >> 1
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w := (data[1] & 0b1) == 1 ? "w" : "b"
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@ -169,7 +169,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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decode_data :: proc(inst_list: ^[dynamic]Instruction, data: []u8, bytes_to_read: int) {
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idx := 0
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has_segment: Maybe(Register)
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has_segment: Maybe(RegisterId)
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has_lock: bool
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for idx < bytes_to_read {
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instruction: Instruction
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@ -203,7 +203,7 @@ decode_data :: proc(inst_list: ^[dynamic]Instruction, data: []u8, bytes_to_read:
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continue
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} else if inst.opname == .SEGMENT {
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reg := (curr_byte & 0b11000) >> 3
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has_segment = CPU.registers[SEGMENT_REGISTER_START+reg]
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has_segment = RegisterId { idx = int(SEGMENT_REGISTER_START+reg) }
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idx += 1
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continue
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} else if inst.opname == .AAM {
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@ -4,34 +4,40 @@ import "core:os"
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import "core:fmt"
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import "core:math"
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import "core:strings"
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import "core:reflect"
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get_operand_value :: proc(operand: Operand) -> u16 {
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#partial switch opr in operand {
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case Immediate:
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return opr.value
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case RegisterId:
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reg_val := CPU.registers[opr.idx]
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switch opr.access {
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case .Low, .High:
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val := opr.access == .Low ? CPU.registers[opr.id].value.low : CPU.registers[opr.id].value.high
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return u16(val)
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return u16(opr.access == .Low ? reg_val.low : reg_val.high)
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case .Full:
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return CPU.registers[opr.id].value.full
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return reg_val.full
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}
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}
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return 0
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}
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set_register_value :: proc(reg_id: RegisterId, value: u16) {
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switch reg_id.access {
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set_register_value :: proc(reg: RegisterId, value: u16) {
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switch reg.access {
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case .Low:
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CPU.registers[reg_id.id].value.low = u8(value)
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CPU.registers[reg.idx].low = u8(value)
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case .High:
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CPU.registers[reg_id.id].value.high = u8(value)
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CPU.registers[reg.idx].high = u8(value)
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case .Full:
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CPU.registers[reg_id.id].value.full = u16(value)
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CPU.registers[reg.idx].full = u16(value)
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}
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}
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get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
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reg,_ := reflect.enum_from_name(Register, name)
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return &cpu.registers[int(reg)]
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}
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check_zero_flag :: proc(value: u16) {
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CPU.flags.ZF = value == 0
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}
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@ -48,19 +54,19 @@ execute_instruction :: proc(inst: Instruction) {
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set_register_value(reg, src_val)
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case .ADD:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.id].value.full + src_val
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val := CPU.registers[reg.idx].full + src_val
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set_register_value(reg, val)
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check_zero_flag(val)
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check_sign_flag(val)
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case .SUB:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.id].value.full - src_val
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val := CPU.registers[reg.idx].full - src_val
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set_register_value(reg, val)
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check_zero_flag(val)
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check_sign_flag(val)
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case .CMP:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.id].value.full - src_val
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val := CPU.registers[reg.idx].full - src_val
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check_zero_flag(val)
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check_sign_flag(val)
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}
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@ -37,7 +37,7 @@ calculate_effective_address :: proc(r_m: u8) -> string {
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return val
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}
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get_memory_string :: proc(memoryAddr: MemoryAddr, has_segment: Maybe(Register)) -> string {
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get_memory_string :: proc(memoryAddr: MemoryAddr, has_segment: Maybe(RegisterId)) -> string {
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disp: string
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switch value in memoryAddr.displacement {
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case None:
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@ -53,7 +53,7 @@ get_memory_string :: proc(memoryAddr: MemoryAddr, has_segment: Maybe(Register))
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}
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seg_string: string
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if segreg, ok := has_segment.?; ok {
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seg_string = fmt.aprintf("%s:", segreg.fullname)
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seg_string = fmt.aprintf("%s:", get_register_name(segreg))
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}
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text := fmt.aprintf("%s[%s%s]", seg_string, calculate_effective_address(memoryAddr.addr_id), disp)
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return text
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@ -78,14 +78,14 @@ get_register_name :: proc(reg_id: RegisterId) -> string {
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low_names := [?]string{"al", "cl", "dl", "bl"}
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high_names := [?]string{"ah", "ch", "dh", "bh"}
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switch reg_id.access {
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case .Full: return CPU.registers[reg_id.id].fullname
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case .Low: return low_names[reg_id.id]
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case .High: return high_names[reg_id.id % 4]
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case .Full: return reflect.enum_string(Register(reg_id.idx))
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case .Low: return low_names[reg_id.idx]
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case .High: return high_names[reg_id.idx % 4]
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}
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return ""
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}
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get_operand_string :: proc(operand: Operand, has_segment: Maybe(Register)) -> string {
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get_operand_string :: proc(operand: Operand, has_segment: Maybe(RegisterId)) -> string {
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string_val: string
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switch val in operand {
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case None:
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@ -106,7 +106,7 @@ get_operand_string :: proc(operand: Operand, has_segment: Maybe(Register)) -> st
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case DirectAddress:
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seg_string: string
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if segreg, ok := has_segment.?; ok {
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seg_string = fmt.aprintf("%s:", segreg.fullname)
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seg_string = fmt.aprintf("%s:", get_register_name(segreg))
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}
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string_val = fmt.aprintf("%s[%d]", seg_string, val)
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case Jump:
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44
sim8086.odin
44
sim8086.odin
@ -1,32 +1,15 @@
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package sim_8086
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import "core:os"
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import "core:path"
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import path "core:path/filepath"
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import "core:fmt"
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import "core:math"
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import "core:strings"
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CPU := Cpu {
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registers = [12]Register {
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{fullname = "ax", code = 0b000},
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{fullname = "cx", code = 0b001},
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{fullname = "dx", code = 0b010},
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{fullname = "bx", code = 0b011},
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{fullname = "sp", code = 0b100},
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{fullname = "bp", code = 0b101},
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{fullname = "si", code = 0b110},
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{fullname = "di", code = 0b111},
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{fullname = "es", code = 0b000},
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{fullname = "cs", code = 0b001},
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{fullname = "ss", code = 0b010},
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{fullname = "ds", code = 0b011},
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},
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memory = make([dynamic]u8, 65536),
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}
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variable_port := CPU.registers[2]
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main :: proc() {
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f,err := os.open(os.args[1])
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if err != os.ERROR_NONE {
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@ -59,22 +42,23 @@ main :: proc() {
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}
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if what_to_print == "registers" || what_to_print == "all" {
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print_reg :: proc(reg: Register) {
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full := fmt.aprintf("%s: %d ", reg.fullname, reg.value.full)
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hex := fmt.aprintf("0x%04x ", reg.value.full)
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for reg,i in CPU.registers {
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full := fmt.aprintf("%s: %d ", get_register_name(RegisterId{idx=i}), reg.full)
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hex := fmt.aprintf("0x%04x ", reg.full)
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fmt.printf("%s %*[1]s %s %*[4]s %08b %08b",
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full, 18 - len(full), "|", hex, 10 - len(hex), "|", reg.value.high, reg.value.low)
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full, 18 - len(full), "|", hex, 10 - len(hex), "|", reg.high, reg.low)
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fmt.println()
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}
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for reg in CPU.registers {
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print_reg(reg)
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}
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// fmt.println("Checking Against Expected State")
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// fmt.println(os.args[1])
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// path := path.base_no_ext(os.args[1])
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// fmt.println(path)
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// extract_expected_cpu_state(path)
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path,ok := strings.replace(os.args[1], ".bin", ".txt", 1)
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expected_cpu,_ := extract_expected_cpu_state(path)
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for reg,i in expected_cpu.registers {
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if CPU.registers[i].full != reg.full {
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name := get_register_name(RegisterId{idx=i})
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msg := "%s register does not match - Expected %04x | Actual %04x"
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fmt.eprintfln(msg, name, reg.full, CPU.registers[i].full)
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}
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}
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}
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if what_to_print == "instructions" || what_to_print == "all" {
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print_instructions_stdout(instructions_list[:])
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54
testing.odin
54
testing.odin
@ -4,35 +4,41 @@ import "core:os"
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import "core:fmt"
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import "core:math"
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import "core:strings"
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import "core:text/regex"
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import "core:strconv"
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extract_expected_cpu_state :: proc(listing_num: int) -> (Cpu, bool) {
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extract_expected_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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cpu: Cpu
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// filename := fmt.aprintf("./asm_files/list-%04d.txt", listing_num)
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// fmt.println(filename)
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// data,ok := os.read_entire_file(filename)
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// if !ok {
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// return cpu, false
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// }
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// defer delete(data)
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data,ok := os.read_entire_file(filename)
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if !ok {
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return cpu, false
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}
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defer delete(data)
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// content := string(data)
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// lines := strings.split(content, "\n")
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// defer delete(lines)
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content := string(data)
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lines := strings.split(content, "\n")
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defer delete(lines)
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// for line in lines {
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// for c in line {
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// if c != ' ' {
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// continue
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// } else {
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// fmt.print(c)
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// }
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// }
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// fmt.println()
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// }
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for line in lines {
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space_count := 0
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for c,i in line {
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if space_count == 0 && c != ' ' {
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break
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} else if c == ' ' {
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space_count += 1
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} else {
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if line[i:i+5] != "flags" {
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reg_name := line[i:i+2]
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reg_value := get_cpu_register_by_name(&cpu, reg_name)
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hex_string := line[i+6:i+10]
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if hex_num,ok := strconv.parse_int(hex_string, 16); ok {
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reg_value^.full = u16(hex_num)
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}
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}
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break
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}
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}
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}
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// cpu.registers[]
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return cpu, true
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}
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35
types.odin
35
types.odin
@ -1,14 +1,25 @@
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package sim_8086
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Register :: struct {
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fullname: string,
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value: struct #raw_union {
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using _: struct {
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low, high: byte,
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},
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full: u16,
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Register :: enum {
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ax,
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cx,
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dx,
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bx,
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sp,
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bp,
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si,
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di,
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es,
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cs,
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ss,
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ds,
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}
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RegisterValue :: struct #raw_union {
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using _: struct {
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low, high: byte,
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},
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code: u8,
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full: u16,
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}
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Flags :: struct {
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@ -34,14 +45,14 @@ Displacement :: union {
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}
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RegisterAccess :: enum {
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Full,
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Low,
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High,
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Full,
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}
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RegisterId :: struct {
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idx: int,
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access: RegisterAccess,
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id: int,
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}
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ImmediateSize :: enum {
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Signed8,
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@ -125,7 +136,7 @@ Instruction :: struct {
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indirect_intersegment: bool,
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// TODO: This is trickier than I thought, it's more than just the one instruction
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// that uses it
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has_segment: Maybe(Register),
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has_segment: Maybe(RegisterId),
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has_lock: bool,
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bytes_read: int,
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raw_data: []u8,
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@ -134,7 +145,7 @@ Instruction :: struct {
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Cpu :: struct {
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flags: Flags,
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registers: [12]Register,
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registers: [12]RegisterValue,
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memory: [dynamic]u8,
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total_bytes_processed: int
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}
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