Change how we detect explicit word sizes, fix data_idx

This commit is contained in:
Joseph Ferano 2025-02-23 12:05:56 +07:00
parent c1799fcac2
commit 1f9837b256

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@ -102,7 +102,6 @@ InstructionInfo :: struct {
has_accumulator: bool, has_accumulator: bool,
has_segreg: bool, has_segreg: bool,
has_flip: bool, has_flip: bool,
has_explicit_size: bool,
has_sign_extension: bool, has_sign_extension: bool,
is_jump: bool, is_jump: bool,
} }
@ -114,7 +113,7 @@ instructions := [?]InstructionInfo {
{ opname = .MOV, desc = "Register/memory to/from register", mask = 0b11111100, encoding = 0b10001000, { opname = .MOV, desc = "Register/memory to/from register", mask = 0b11111100, encoding = 0b10001000,
reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true }, reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true },
{ opname = .MOV, desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b11000110, { opname = .MOV, desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b11000110,
has_data = true, has_address = true, word_size = LastBit{}, has_explicit_size = true }, has_data = true, has_address = true, word_size = LastBit{}, },
{ opname = .MOV, desc = "Immediate to register", mask = 0b11110000, encoding = 0b10110000, { opname = .MOV, desc = "Immediate to register", mask = 0b11110000, encoding = 0b10110000,
reg_info = reg_first_last, has_data = true, word_size = FourthBit{} }, reg_info = reg_first_last, has_data = true, word_size = FourthBit{} },
{ opname = .MOV, desc = "Memory to accumulator", mask = 0b11111110, encoding = 0b10100000, { opname = .MOV, desc = "Memory to accumulator", mask = 0b11111110, encoding = 0b10100000,
@ -130,7 +129,7 @@ instructions := [?]InstructionInfo {
{ opname = .TBD, desc = "Immediate to register/memory", mask = 0b11111100, encoding = 0b10000000, { opname = .TBD, desc = "Immediate to register/memory", mask = 0b11111100, encoding = 0b10000000,
opcode_id = .Second, has_data = true, has_address = true, opcode_id = .Second, has_data = true, has_address = true,
word_size = LastBit{}, has_sign_extension = true }, word_size = LastBit{}, has_sign_extension = true },
{ opname = .TBD, desc = "Immediate to accumulator", mask = 0b11111110, encoding = 0b00000100, { opname = .TBD, desc = "Immediate to accumulator", mask = 0b11000100, encoding = 0b00000100,
word_size = LastBit{}, has_data = true }, word_size = LastBit{}, has_data = true },
{ opname = .JE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110100, is_jump = true}, { opname = .JE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110100, is_jump = true},
@ -228,7 +227,7 @@ OperandType :: union {
} }
inst_map := make(map[u8]InstructionInfo) inst_map := make(map[u8]InstructionInfo)
RIGHT_ALIGN_AMOUNT := 30 RIGHT_ALIGN_AMOUNT := 35
calculate_effective_address :: proc(r_m: u8) -> string { calculate_effective_address :: proc(r_m: u8) -> string {
val: string val: string
@ -389,6 +388,8 @@ main :: proc() {
is_word: bool is_word: bool
is_immediate := false is_immediate := false
flip_dst := false flip_dst := false
has_memory_addr := false
has_immediate := false
rm: u8 rm: u8
mod: u8 mod: u8
reg: u8 reg: u8
@ -421,13 +422,18 @@ main :: proc() {
if rm == 0b110 { if rm == 0b110 {
lhs2 = (Accumulator)(get_i16(data[idx+2:])) lhs2 = (Accumulator)(get_i16(data[idx+2:]))
processed += 2 processed += 2
data_idx += 2
} else { } else {
lhs2 = MemoryAddr{ addr_id = rm , displacement = None{} } lhs2 = MemoryAddr{ addr_id = rm , displacement = None{} }
} }
// NOTE: This also works when it's an Accumulator apparently
has_memory_addr = true
} else if mod == 1 { } else if mod == 1 {
lhs2 = MemoryAddr{ addr_id = rm , displacement = (i8)(data[idx+2]) } lhs2 = MemoryAddr{ addr_id = rm , displacement = (i8)(data[idx+2]) }
has_memory_addr = true
} else if mod == 2 { } else if mod == 2 {
lhs2 = MemoryAddr{ addr_id = rm , displacement = get_i16(data[idx+2:]) } lhs2 = MemoryAddr{ addr_id = rm , displacement = get_i16(data[idx+2:]) }
has_memory_addr = true
} else if mod == 3 { } else if mod == 3 {
lhs2 = (RegisterId)(registers[rm].code) lhs2 = (RegisterId)(registers[rm].code)
} }
@ -441,6 +447,7 @@ main :: proc() {
} }
processed += word_signed ? 2 : 1 processed += word_signed ? 2 : 1
rhs2 = (OperandType)(word_signed ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx])) rhs2 = (OperandType)(word_signed ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx]))
has_immediate = true
} else if instruction.has_accumulator { } else if instruction.has_accumulator {
processed += is_word ? 2 : 1 processed += is_word ? 2 : 1
rhs2 = (OperandType)(is_word ? (Accumulator)(get_i16(data[data_idx:])) : (Accumulator)(data[data_idx])) rhs2 = (OperandType)(is_word ? (Accumulator)(get_i16(data[data_idx:])) : (Accumulator)(data[data_idx]))
@ -454,17 +461,15 @@ main :: proc() {
lhs := get_memory_type_string(lhs2, is_word) lhs := get_memory_type_string(lhs2, is_word)
rhs := get_memory_type_string(rhs2, is_word) rhs := get_memory_type_string(rhs2, is_word)
size_string := instruction.has_explicit_size ? is_word ? "word " : "byte " : "" size_string := has_immediate && has_memory_addr ? is_word ? "word " : "byte " : ""
full_inst: string full_inst: string
opname: string opname: string
if instruction.opname == .TBD { if instruction.opname == .TBD {
opid: u8 if instruction.opcode_id == .Second {
if instruction.opcode_id == .First { opname = strings.to_lower(fmt.aprintf("%s", get_opname(data[idx+1])))
opid = curr_byte & 0b00_111_000 >> 3 } else {
} else if instruction.opcode_id == .Second { opname = strings.to_lower(fmt.aprintf("%s", get_opname(curr_byte)))
opid = data[idx+1] & 0b00_111_000 >> 3
} }
opname = strings.to_lower(fmt.aprintf("%s", get_opname(opid)))
} else { } else {
opname = strings.to_lower(fmt.aprintf("%s", instruction.opname)) opname = strings.to_lower(fmt.aprintf("%s", instruction.opname))
} }
@ -476,7 +481,12 @@ main :: proc() {
full_inst = fmt.aprintf("%s %s", strings.to_lower(opname), "label") full_inst = fmt.aprintf("%s %s", strings.to_lower(opname), "label")
processed += 1 processed += 1
} else { } else {
full_inst = fmt.aprintf("%s %s, %s%s", strings.to_lower(opname), lhs, size_string, rhs) opname = strings.to_lower(opname)
if opname == "mov" {
full_inst = fmt.aprintf("%s %s, %s%s", opname, lhs, size_string, rhs)
} else {
full_inst = fmt.aprintf("%s %s%s, %s", opname, size_string, lhs, rhs)
}
} }
fmt.printf("%s %*[1]s", full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;") fmt.printf("%s %*[1]s", full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;")
for i in 0..<processed { for i in 0..<processed {