Types and instruction specifications moved to decode.h
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a0ed11416e
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26c07aee61
2
Makefile
2
Makefile
@ -9,7 +9,7 @@ bin_files = $(patsubst %.asm,%.bin,$(asm_files))
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all: decode asm_files
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decode: decode.c lib.h
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decode: decode.c decode.h lib.h
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$(CC) $(CFLAGS) $< -o $@
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asm_files: $(bin_files)
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160
decode.c
160
decode.c
@ -1,130 +1,10 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include "lib.h"
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#include <sys/stat.h>
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#include <string.h>
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#include <assert.h>
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enum InstructionType
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{
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INST_MOV_REG_REG = 0b10001000,
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// INST_MOV_REG_REG = 0b10001000,
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// INST_MOV_REG_REG = 0b10001000,
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};
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enum Mode
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{
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MODE_MEM_NO_DIS = 0b00,
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MODE_MEM_DIS_08 = 0b01,
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MODE_MEM_DIS_16 = 0b10,
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MODE_RGSTR_MODE = 0b11,
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};
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typedef struct Register
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{
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char* fullname;
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char* bytename;
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union {
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struct {
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char low;
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char high;
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};
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u16 full;
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} value;
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u8 code;
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} Register;
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Register registers[8] = {
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{.code = 0b000, .fullname = "ax", .bytename = "al"},
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{.code = 0b001, .fullname = "cx", .bytename = "cl"},
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{.code = 0b010, .fullname = "dx", .bytename = "dl"},
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{.code = 0b011, .fullname = "bx", .bytename = "bl"},
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{.code = 0b100, .fullname = "sp", .bytename = "ah"},
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{.code = 0b101, .fullname = "bp", .bytename = "ch"},
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{.code = 0b110, .fullname = "si", .bytename = "dh"},
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{.code = 0b111, .fullname = "di", .bytename = "bh"},
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};
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enum OperandType {OPR_T_MEMORY, OPR_T_REGISTER, OPR_T_IMMEDIATE, OPR_T_DIRADDR};
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typedef struct Operand
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{
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enum OperandType tag;
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union {
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struct Mem {
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char *eac_name;
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i16 displacement;
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u8 mode;
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} mem;
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struct Reg {
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Register value;
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bool wide;
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} reg;
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struct Imm {
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i16 value;
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u8 direct;
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} imm;
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struct DirAddr {
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i16 value;
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} dir_addr;
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};
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} Operand;
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enum ParseRegType { P_REG_NONE, P_REG_MASK, P_REG_FIXED };
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typedef struct ParseReg
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{
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enum ParseRegType tag;
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union {
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u8 none;
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u8 mask;
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u8 fixed;
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};
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} ParseReg;
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typedef struct InstFormat
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{
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u16 id;
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char *name;
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ParseReg parse_reg;
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u8 inst_enc;
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u8 mask_inst;
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u8 mask_w;
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bool has_operands;
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bool has_displacement;
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bool has_data;
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bool has_d;
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bool has_w;
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bool has_mod;
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bool has_rm;
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bool has_s;
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bool has_SR;
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} InstFormat;
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typedef struct ParsedInstruction
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{
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u16 id;
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char *name;
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u16_opt data;
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u16_opt displacement;
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u8_opt w;
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u8_opt d;
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u8_opt s;
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u8_opt mod;
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u8_opt reg;
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u8_opt rm;
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u8_opt SR;
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u8 is_data_addr;
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u8 bytes_read;
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} ParsedInstruction;
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typedef struct Instruction
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{
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Operand src_opr;
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Operand dst_opr;
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i16 data;
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char *operation;
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u16 id;
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} Instruction;
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#include "lib.h"
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#include "decode.h"
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/// Get Effective Address Calculation Registers
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char* get_eac_register(char rm)
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@ -169,42 +49,6 @@ static u8 mask_and_shift(u8 value, u8 mask)
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return value;
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}
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InstFormat inst_formats[] =
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{
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////////
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// MOV
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////////
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// Register/memory to/from register
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{.id=1, .name="mov", .inst_enc=0b10001000, .mask_inst=0x3, .mask_w=0x1,
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.has_operands=true, .has_displacement=true, .has_d=true, .has_w=true,
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.has_mod=true, .has_rm=true, .parse_reg={.tag = P_REG_MASK, .mask=0b00111000} },
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// Immediate to register/memory
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{.id=2, .name="mov", .inst_enc=0b11000110, .mask_inst=0x1, .mask_w=0x1, .has_operands=true,
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.has_displacement=true, .has_data=true, .has_w=true, .has_mod=true, .has_rm=true},
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// Immediate to register
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{.id=3, .name="mov", .inst_enc=0b10110000, .mask_inst=0xF, .mask_w=0x8,
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.parse_reg={.tag = P_REG_MASK, .mask=0b00000111}, .has_data=true, .has_w=true},
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// Memory to accumulator | Accumulator to memory using the `d` bit
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// even though the manual doesn't specify it
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{.id=4, .name="mov", .inst_enc=0b10100000, .mask_inst=0x3, .mask_w=0x1, .has_data=true,
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.has_w=true, .has_d=true, .parse_reg={.tag = P_REG_FIXED, .fixed=0x0}},
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// Register/memory to segment register and inverse using the `d` bit
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{.id=5, .name="mov", .inst_enc=0b10001100, .mask_inst=0x3, .has_SR=true, .has_d=true,
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.has_displacement=true, .has_mod=true, .has_rm=true},
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////////
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// ADD
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////////
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// Reg/memory with register or either
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{.id=6, .name="add", .inst_enc=0b00000000, .mask_inst=0x3, .has_displacement=true,
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.mask_w=0x1, .has_operands=true, .has_w=true, .has_d=true, .has_mod=true,
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.has_rm=true, .parse_reg={.tag = P_REG_MASK, .mask=0b00111000}},
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// Immediate to register/memory
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{.id=7, .name="add", .inst_enc=0b10000000, .mask_inst=0x3, .mask_w=0x1, .has_w=true,
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.has_operands=true, .has_displacement=true, .has_data=true, .has_mod=true, .has_rm=true},
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{.id=8, .name="add", .inst_enc=0b00000100, .mask_inst=0x1, .mask_w=0x1,
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.has_data=true, .has_w=true, .parse_reg={.tag = P_REG_FIXED, .fixed=0x0}},
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};
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ParsedInstruction parse_instruction(u8* buf)
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{
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u8 inst = buf[0];
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151
decode.h
Normal file
151
decode.h
Normal file
@ -0,0 +1,151 @@
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#include "lib.h"
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enum Mode
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{
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MODE_MEM_NO_DIS = 0b00,
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MODE_MEM_DIS_08 = 0b01,
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MODE_MEM_DIS_16 = 0b10,
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MODE_RGSTR_MODE = 0b11,
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};
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typedef struct Register
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{
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char* fullname;
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char* bytename;
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union {
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struct {
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char low;
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char high;
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};
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u16 full;
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} value;
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u8 code;
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} Register;
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Register registers[8] = {
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{.code = 0b000, .fullname = "ax", .bytename = "al"},
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{.code = 0b001, .fullname = "cx", .bytename = "cl"},
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{.code = 0b010, .fullname = "dx", .bytename = "dl"},
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{.code = 0b011, .fullname = "bx", .bytename = "bl"},
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{.code = 0b100, .fullname = "sp", .bytename = "ah"},
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{.code = 0b101, .fullname = "bp", .bytename = "ch"},
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{.code = 0b110, .fullname = "si", .bytename = "dh"},
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{.code = 0b111, .fullname = "di", .bytename = "bh"},
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};
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enum OperandType {OPR_T_MEMORY, OPR_T_REGISTER, OPR_T_IMMEDIATE, OPR_T_DIRADDR};
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typedef struct Operand
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{
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enum OperandType tag;
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union {
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struct Mem {
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char *eac_name;
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i16 displacement;
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u8 mode;
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} mem;
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struct Reg {
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Register value;
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bool wide;
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} reg;
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struct Imm {
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i16 value;
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u8 direct;
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} imm;
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struct DirAddr {
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i16 value;
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} dir_addr;
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};
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} Operand;
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enum ParseRegType { P_REG_NONE, P_REG_MASK, P_REG_FIXED };
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typedef struct ParseReg
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{
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enum ParseRegType tag;
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union {
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u8 none;
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u8 mask;
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u8 fixed;
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};
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} ParseReg;
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typedef struct InstFormat
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{
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u16 id;
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char *name;
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ParseReg parse_reg;
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u8 inst_enc;
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u8 mask_inst;
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u8 mask_w;
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bool has_operands;
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bool has_displacement;
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bool has_data;
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bool has_d;
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bool has_w;
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bool has_mod;
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bool has_rm;
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bool has_s;
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bool has_SR;
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} InstFormat;
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typedef struct ParsedInstruction
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{
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u16 id;
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char *name;
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u16_opt data;
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u16_opt displacement;
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u8_opt w;
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u8_opt d;
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u8_opt s;
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u8_opt mod;
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u8_opt reg;
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u8_opt rm;
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u8_opt SR;
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u8 is_data_addr;
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u8 bytes_read;
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} ParsedInstruction;
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typedef struct Instruction
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{
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Operand src_opr;
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Operand dst_opr;
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i16 data;
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char *operation;
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u16 id;
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} Instruction;
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InstFormat inst_formats[] =
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{
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////////
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// MOV
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////////
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// Register/memory to/from register
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{.id=1, .name="mov", .inst_enc=0b10001000, .mask_inst=0x3, .mask_w=0x1,
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.has_operands=true, .has_displacement=true, .has_d=true, .has_w=true,
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.has_mod=true, .has_rm=true, .parse_reg={.tag = P_REG_MASK, .mask=0b00111000} },
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// Immediate to register/memory
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{.id=2, .name="mov", .inst_enc=0b11000110, .mask_inst=0x1, .mask_w=0x1, .has_operands=true,
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.has_displacement=true, .has_data=true, .has_w=true, .has_mod=true, .has_rm=true},
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// Immediate to register
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{.id=3, .name="mov", .inst_enc=0b10110000, .mask_inst=0xF, .mask_w=0x8,
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.parse_reg={.tag = P_REG_MASK, .mask=0b00000111}, .has_data=true, .has_w=true},
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// Memory to accumulator | Accumulator to memory using the `d` bit
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// even though the manual doesn't specify it
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{.id=4, .name="mov", .inst_enc=0b10100000, .mask_inst=0x3, .mask_w=0x1, .has_data=true,
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.has_w=true, .has_d=true, .parse_reg={.tag = P_REG_FIXED, .fixed=0x0}},
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// Register/memory to segment register and inverse using the `d` bit
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{.id=5, .name="mov", .inst_enc=0b10001100, .mask_inst=0x3, .has_SR=true, .has_d=true,
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.has_displacement=true, .has_mod=true, .has_rm=true},
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////////
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// ADD
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////////
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// Reg/memory with register or either
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{.id=6, .name="add", .inst_enc=0b00000000, .mask_inst=0x3, .has_displacement=true,
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.mask_w=0x1, .has_operands=true, .has_w=true, .has_d=true, .has_mod=true,
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.has_rm=true, .parse_reg={.tag = P_REG_MASK, .mask=0b00111000}},
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// Immediate to register/memory
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{.id=7, .name="add", .inst_enc=0b10000000, .mask_inst=0x3, .mask_w=0x1, .has_w=true,
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.has_operands=true, .has_displacement=true, .has_data=true, .has_mod=true, .has_rm=true},
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{.id=8, .name="add", .inst_enc=0b00000100, .mask_inst=0x1, .mask_w=0x1,
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.has_data=true, .has_w=true, .parse_reg={.tag = P_REG_FIXED, .fixed=0x0}},
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};
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