Generalizing data and operand bracketing, to make add instrunction work
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bc0a8b65eb
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@ -61,8 +61,9 @@ InstructionInfo :: struct {
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has_displacement: bool,
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has_segreg: bool,
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has_flip: bool,
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has_bracketed_immediate: bool,
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has_explicit_size: bool,
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has_accumulator: bool,
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has_sign_extension: bool,
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}
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reg_first_last := RegInfo{ in_first_byte = true, shift_offset = 0 }
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@ -74,22 +75,28 @@ instructions := [?]InstructionInfo {
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word_size = LastBit{}, has_flip = true },
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{ name = "mov", desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b11000110,
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has_mod_rm = true, reg_info = nil, has_data = true, has_displacement = true,
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word_size = LastBit{}, has_explicit_size = true },
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word_size = LastBit{}, has_bracketed_immediate = false, has_explicit_size = true },
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{ name = "mov", desc = "Immediate to register", mask = 0b11110000, encoding = 0b10110000,
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has_mod_rm = false, reg_info = reg_first_last, has_data = true, has_displacement = false,
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word_size = FourthBit{} },
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{ name = "mov", desc = "Memory to accumulator", mask = 0b11111110, encoding = 0b10100000,
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has_mod_rm = false, reg_info = nil, has_data = true, has_displacement = false, has_flip = true,
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word_size = LastBit{}, has_accumulator = true },
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word_size = LastBit{}, has_bracketed_immediate = true },
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{ name = "mov", desc = "Accumulator to memory", mask = 0b11111110, encoding = 0b10100010,
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has_mod_rm = false, reg_info = nil, has_data = true, has_displacement = false, has_flip = true,
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word_size = LastBit{}, has_accumulator = true },
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word_size = LastBit{}, has_bracketed_immediate = true },
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{ name = "mov", desc = "Register/memory to segment register", mask = 0b11111111, encoding = 0b10001110,
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has_mod_rm = true, reg_info = nil, has_segreg = true, has_displacement = true,
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word_size = None{} },
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{ name = "mov", desc = "Segment register to register/memory", mask = 0b11111111, encoding = 0b10001100,
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has_mod_rm = true, reg_info = nil, has_segreg = true, has_displacement = true,
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word_size = None{} },
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{ name = "add", desc = "Register/memory to/from register", mask = 0b11111100, encoding = 0b00000000,
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has_mod_rm = true, reg_info = reg_second_middle, has_data = false, has_displacement = true,
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word_size = LastBit{}, has_flip = true },
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{ name = "add", desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b10000000,
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has_mod_rm = true, reg_info = nil, has_data = true, has_displacement = true,
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word_size = LastBit{}, has_sign_extension = true },
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}
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None :: struct {}
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@ -129,17 +136,11 @@ MemoryAddr :: struct {
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addr_id: u8,
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displacement: Displacement
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}
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DirectAddress :: distinct i16
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Accumulator8 :: distinct i8
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Accumulator16 :: distinct i16
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OperandType :: union {
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RegisterId,
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Immediate8,
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Immediate16,
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MemoryAddr,
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DirectAddress,
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Accumulator8,
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Accumulator16,
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}
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inst_map := make(map[u8]InstructionInfo)
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@ -186,24 +187,19 @@ get_memory_string :: proc(memoryAddr: MemoryAddr) -> string {
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return text
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}
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get_memory_type_string :: proc(mem_type: OperandType, is_word: bool) -> string {
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get_memory_type_string :: proc(mem_type: OperandType, is_word: bool, bracketed: bool) -> string {
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string_val: string
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switch val in mem_type {
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case RegisterId:
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return is_word ? registers[val].fullname : registers[val].bytename
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string_val = is_word ? registers[val].fullname : registers[val].bytename
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case Immediate8:
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return fmt.aprintf("%d", val)
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string_val = fmt.aprintf(bracketed ? "[%d]" : "%d", val)
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case Immediate16:
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return fmt.aprintf("%d", val)
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string_val = fmt.aprintf(bracketed ? "[%d]" : "%d", val)
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case MemoryAddr:
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return get_memory_string(val)
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case DirectAddress:
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return fmt.aprintf("[%d]", val)
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case Accumulator8:
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return fmt.aprintf("[%d]", val)
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case Accumulator16:
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return fmt.aprintf("[%d]", val)
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string_val = get_memory_string(val)
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}
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return ""
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return string_val
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}
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get_i16 :: proc(data: []u8) -> i16 {
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@ -285,7 +281,6 @@ main :: proc() {
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processed := 1
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curr_byte := data[idx]
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instruction, ok := try_find_instruction(curr_byte)
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if !ok {
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txt := "unknown instruction"
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@ -299,6 +294,7 @@ main :: proc() {
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is_word: bool
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is_immediate := false
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flip_dst := false
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bracket_operand := instruction.has_bracketed_immediate
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rm: u8
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mod: u8
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reg: u8
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@ -318,15 +314,19 @@ main :: proc() {
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reg = (b >> reg_info.shift_offset) & 0b111
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}
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data_idx := idx + 1
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if instruction.has_mod_rm {
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mod = data[idx+1] >> 6
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rm = data[idx+1] & 0b00000111
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data_idx += 1 + ((int)(mod) % 3)
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processed += 1 + ((int)(mod) % 3)
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if mod == 0 {
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if rm == 0b110 {
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lhs2 = (DirectAddress)(get_i16(data[idx+2:]))
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lhs2 = (Immediate16)(get_i16(data[idx+2:]))
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bracket_operand = true
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processed += 2
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} else {
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lhs2 = MemoryAddr{ addr_id = rm , displacement = None{} }
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@ -338,32 +338,25 @@ main :: proc() {
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} else if mod == 3 {
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lhs2 = (RegisterId)(registers[rm].code)
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}
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if instruction.has_explicit_size {
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imm_idx := idx + 2 + ((int)(mod) % 3)
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rhs2 = (OperandType)(is_word ? (Immediate16)(get_i16(data[imm_idx:])) : (Immediate8)(data[imm_idx]))
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processed += is_word ? 2 : 1
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} else {
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rhs2 = (RegisterId)(reg)
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}
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} else {
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lhs2 = (RegisterId)(registers[reg].code)
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if instruction.has_accumulator {
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rhs2 = (OperandType)(is_word ? ((Accumulator16)(get_i16(data[idx+1:]))) : ((Accumulator8)(data[idx+1])))
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} else {
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rhs2 = (OperandType)(is_word ? ((Immediate16)(get_i16(data[idx+1:]))) : ((Immediate8)(data[idx+1])))
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}
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}
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if instruction.has_data {
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processed += is_word ? 2 : 1
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rhs2 = (OperandType)(is_word ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx]))
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} else {
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rhs2 = (RegisterId)(reg)
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}
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if flip_dst {
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lhs2, rhs2 = rhs2, lhs2
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}
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lhs := get_memory_type_string(lhs2, is_word)
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rhs := get_memory_type_string(rhs2, is_word)
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lhs := get_memory_type_string(lhs2, is_word, bracket_operand)
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rhs := get_memory_type_string(rhs2, is_word, bracket_operand)
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size_string := instruction.has_explicit_size ? is_word ? "word " : "byte " : ""
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full_inst := fmt.aprintf("%s %s, %s%s", instruction.name, lhs, size_string, rhs)
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fmt.printf("%s %*[1]s a", full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;")
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fmt.printf("%s %*[1]s", full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;")
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for i in 0..<processed {
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fmt.printf(" %08b", data[idx + i])
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}
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