Decode then check reference flags, change registers and flags to use enumerated arrays
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cd5eada115
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5cf4768b80
@ -80,11 +80,11 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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case .SecondByteLast3: reg = data[1] & 0b111
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}
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if opinfo == .SegmentRegister {
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operand = (RegisterId){idx = SEGMENT_REGISTER_START + (int)(reg), access = .Full}
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operand = (RegisterId){name = Register(SEGMENT_REGISTER_START + (int)(reg)), access = .Full}
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} else if word {
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operand = RegisterId { idx = (int)(reg), access = .Full }
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operand = RegisterId { name = Register(reg), access = .Full }
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} else {
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operand = RegisterId { idx = (int)(reg % 4), access = reg < 4 ? .Low : .High }
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operand = RegisterId { name = Register(reg % 4), access = reg < 4 ? .Low : .High }
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}
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case .RegisterMemory:
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mod := data[1] >> 6
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@ -107,9 +107,9 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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processed^ += 2
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} else if mod == 3 {
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if word {
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op = RegisterId { idx = (int)(rm), access = .Full }
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op = RegisterId { name = Register(rm), access = .Full }
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} else {
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op = RegisterId { idx = (int)(rm % 4), access = rm < 4 ? .Low : .High }
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op = RegisterId { name = Register(rm % 4), access = rm < 4 ? .Low : .High }
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}
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}
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operand = op
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@ -126,7 +126,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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operand = Immediate { value = u16(data[processed^]), size = .Unsigned8 }
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processed^ += 1
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case .Accumulator:
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operand = RegisterId { idx = 0, access = word ? .Full : .Low }
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operand = RegisterId { name = Register(0), access = word ? .Full : .Low }
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case .DirectAddress:
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// operand = DirectAddress { value = get_i16(data[1:]) }
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operand = (DirectAddress)(get_i16(data[1:]))
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@ -136,10 +136,10 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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// NOTE: In order to mimic the label offset, you have to take the value you got and add two
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operand = (Jump)((i8)(data[1]) + 2)
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case .VariablePort:
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operand = RegisterId { idx = (int)(Register.dx), access = .Full }
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operand = RegisterId { name = Register.dx, access = .Full }
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case .ShiftRotate:
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v_flag := data[0] & 0b10 != 0
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operand = v_flag ? RegisterId { idx = 1, access = .Low } : Immediate { value = 1 }
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operand = v_flag ? RegisterId { name = Register(1), access = .Low } : Immediate { value = 1 }
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case .Repeat:
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bits := (data[1] & 0b1110) >> 1
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w := (data[1] & 0b1) == 1 ? "w" : "b"
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@ -203,7 +203,7 @@ decode_data :: proc(inst_list: ^[dynamic]Instruction, data: []u8, bytes_to_read:
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continue
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} else if inst.opname == .SEGMENT {
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reg := (curr_byte & 0b11000) >> 3
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has_segment = RegisterId { idx = int(SEGMENT_REGISTER_START+reg) }
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has_segment = RegisterId { name = Register(SEGMENT_REGISTER_START+reg) }
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idx += 1
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continue
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} else if inst.opname == .AAM {
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@ -11,7 +11,7 @@ get_operand_value :: proc(operand: Operand) -> u16 {
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case Immediate:
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return opr.value
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case RegisterId:
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reg_val := CPU.registers[opr.idx]
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reg_val := CPU.registers[opr.name]
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switch opr.access {
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case .Low, .High:
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return u16(opr.access == .Low ? reg_val.low : reg_val.high)
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@ -25,25 +25,25 @@ get_operand_value :: proc(operand: Operand) -> u16 {
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set_register_value :: proc(reg: RegisterId, value: u16) {
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switch reg.access {
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case .Low:
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CPU.registers[reg.idx].low = u8(value)
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CPU.registers[reg.name].low = u8(value)
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case .High:
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CPU.registers[reg.idx].high = u8(value)
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CPU.registers[reg.name].high = u8(value)
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case .Full:
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CPU.registers[reg.idx].full = u16(value)
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CPU.registers[reg.name].full = u16(value)
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}
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}
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get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
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reg,_ := reflect.enum_from_name(Register, name)
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return &cpu.registers[int(reg)]
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return &cpu.registers[reg]
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}
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check_zero_flag :: proc(value: u16) {
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CPU.flags.ZF = value == 0
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CPU.flags[.ZF] = value == 0
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}
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check_sign_flag :: proc(value: u16) {
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CPU.flags.SF = value >> 15 == 1
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CPU.flags[.SF] = value >> 15 == 1
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}
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execute_instruction :: proc(inst: Instruction) {
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@ -54,19 +54,19 @@ execute_instruction :: proc(inst: Instruction) {
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set_register_value(reg, src_val)
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case .ADD:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.idx].full + src_val
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val := CPU.registers[reg.name].full + src_val
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set_register_value(reg, val)
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check_zero_flag(val)
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check_sign_flag(val)
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case .SUB:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.idx].full - src_val
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val := CPU.registers[reg.name].full - src_val
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set_register_value(reg, val)
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check_zero_flag(val)
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check_sign_flag(val)
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case .CMP:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.idx].full - src_val
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val := CPU.registers[reg.name].full - src_val
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check_zero_flag(val)
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check_sign_flag(val)
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}
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@ -78,9 +78,9 @@ get_register_name :: proc(reg_id: RegisterId) -> string {
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low_names := [?]string{"al", "cl", "dl", "bl"}
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high_names := [?]string{"ah", "ch", "dh", "bh"}
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switch reg_id.access {
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case .Full: return reflect.enum_string(Register(reg_id.idx))
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case .Low: return low_names[reg_id.idx]
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case .High: return high_names[reg_id.idx % 4]
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case .Full: return reflect.enum_string(reg_id.name)
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case .Low: return low_names[int(reg_id.name)]
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case .High: return high_names[int(reg_id.name) % 4]
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}
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return ""
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}
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31
sim8086.odin
31
sim8086.odin
@ -5,6 +5,7 @@ import path "core:path/filepath"
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import "core:fmt"
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import "core:math"
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import "core:strings"
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import "core:reflect"
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CPU := Cpu {
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memory = make([dynamic]u8, 65536),
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@ -42,21 +43,31 @@ main :: proc() {
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}
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if what_to_print == "registers" || what_to_print == "all" {
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for reg,i in CPU.registers {
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full := fmt.aprintf("%s: %d ", get_register_name(RegisterId{idx=i}), reg.full)
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hex := fmt.aprintf("0x%04x ", reg.full)
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fmt.println("\nRegisters")
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for reg_val,name in CPU.registers {
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full := fmt.aprintf("%s: %d ", name, reg_val.full)
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hex := fmt.aprintf("0x%04x ", reg_val.full)
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fmt.printf("%s %*[1]s %s %*[4]s %08b %08b",
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full, 18 - len(full), "|", hex, 10 - len(hex), "|", reg.high, reg.low)
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full, 18 - len(full), "|", hex, 10 - len(hex), "|", reg_val.high, reg_val.low)
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fmt.println()
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}
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fmt.println("\nFlags")
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for state,flag in CPU.flags {
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fmt.printfln("%c: %d",reflect.enum_string(flag)[0], state ? 1 : 0)
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}
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path,ok := strings.replace(os.args[1], ".bin", ".txt", 1)
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expected_cpu,_ := extract_expected_cpu_state(path)
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for reg,i in expected_cpu.registers {
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if CPU.registers[i].full != reg.full {
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name := get_register_name(RegisterId{idx=i})
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msg := "%s register does not match - Expected %04x | Actual %04x"
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fmt.eprintfln(msg, name, reg.full, CPU.registers[i].full)
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ref_cpu,_ := extract_reference_cpu_state(path)
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for reg_val,name in ref_cpu.registers {
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if CPU.registers[name].full != reg_val.full {
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msg := "%s register does not match reference - Expected %04x | Actual %04x"
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fmt.eprintfln(msg, name, reg_val.full, CPU.registers[name].full)
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}
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}
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for f in Flag {
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if ref_cpu.flags[f] != CPU.flags[f] {
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msg := "%s flag does not match reference - Expected %t | Actual %t"
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fmt.eprintfln(msg, f, ref_cpu.flags[f], CPU.flags[f])
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}
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}
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}
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16
testing.odin
16
testing.odin
@ -5,8 +5,9 @@ import "core:fmt"
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import "core:math"
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import "core:strings"
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import "core:strconv"
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import "core:reflect"
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extract_expected_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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cpu: Cpu
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data,ok := os.read_entire_file(filename)
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@ -27,7 +28,18 @@ extract_expected_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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} else if c == ' ' {
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space_count += 1
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} else {
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if line[i:i+5] != "flags" {
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if line[i:i+5] == "flags" {
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idx := i + 7
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for idx < len(line) {
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flag_name := fmt.tprintf("%cF", line[idx])
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if flag,ok := reflect.enum_from_name(Flag, flag_name); ok {
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cpu.flags[flag] = true
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} else {
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fmt.eprintfln("Error parsing flag enum %s", flag_name)
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}
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idx += 1
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}
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} else {
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reg_name := line[i:i+2]
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reg_value := get_cpu_register_by_name(&cpu, reg_name)
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hex_string := line[i+6:i+10]
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21
types.odin
21
types.odin
@ -22,9 +22,18 @@ RegisterValue :: struct #raw_union {
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full: u16,
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}
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Flags :: struct {
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ZF: bool,
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SF: bool,
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Flag :: enum {
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OF,
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SF,
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ZF,
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AF,
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PF,
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CF,
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// NOTE: These are the control flags, previous are status flags, justing noting in
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// case we have to make that distinction in later modeling
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TF,
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DF,
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IF,
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}
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WordSize :: enum {
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@ -51,7 +60,7 @@ RegisterAccess :: enum {
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}
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RegisterId :: struct {
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idx: int,
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name: Register,
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access: RegisterAccess,
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}
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ImmediateSize :: enum {
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@ -144,8 +153,8 @@ Instruction :: struct {
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}
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Cpu :: struct {
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flags: Flags,
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registers: [12]RegisterValue,
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flags: [Flag]bool,
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registers: [Register]RegisterValue,
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memory: [dynamic]u8,
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total_bytes_processed: int
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}
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