Handle accumulator differently, handle segment registers, handle unary, add instructions
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390fedc848
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782ff93ace
@ -159,36 +159,54 @@ InstructionInfo :: struct {
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reg_info: Maybe(RegInfo),
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has_data: bool,
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has_address: bool,
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has_accumulator: bool,
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uses_accumulator: bool,
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has_segreg: bool,
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has_flip: bool,
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has_sign_extension: bool,
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is_jump: bool,
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is_unary: bool,
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}
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// TODO: Maybe we can get rid of it since I don't have to specify the shift_offset,
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// not like it changes a lot
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reg_first_last := RegInfo{ in_first_byte = true, shift_offset = 0 }
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reg_second_middle := RegInfo{ in_first_byte = false, shift_offset = 3 }
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reg_first_middle := RegInfo{ in_first_byte = true, shift_offset = 3 }
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instructions := [?]InstructionInfo {
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{ opname = .MOV, desc = "Register/memory to/from register", mask = 0b11111100, encoding = 0b10001000,
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{ opname = .MOV, desc = "Register/memory to/from register", mask = 0b11111100, encoding = 0b10001000,
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reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true },
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{ opname = .MOV, desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b11000110,
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{ opname = .MOV, desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b11000110,
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has_data = true, has_address = true, word_size = LastBit{}, },
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{ opname = .MOV, desc = "Immediate to register", mask = 0b11110000, encoding = 0b10110000,
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{ opname = .MOV, desc = "Immediate to register", mask = 0b11110000, encoding = 0b10110000,
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reg_info = reg_first_last, has_data = true, word_size = FourthBit{} },
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{ opname = .MOV, desc = "Memory to accumulator", mask = 0b11111110, encoding = 0b10100000,
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has_flip = true, word_size = LastBit{}, has_accumulator = true },
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{ opname = .MOV, desc = "Accumulator to memory", mask = 0b11111110, encoding = 0b10100010,
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has_flip = true, word_size = LastBit{}, has_accumulator = true },
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{ opname = .MOV, desc = "Register/memory to segment register", mask = 0b11111111, encoding = 0b10001110,
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{ opname = .MOV, desc = "Memory to accumulator", mask = 0b11111110, encoding = 0b10100000,
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has_flip = true, word_size = LastBit{}, uses_accumulator = true },
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{ opname = .MOV, desc = "Accumulator to memory", mask = 0b11111110, encoding = 0b10100010,
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has_flip = true, word_size = LastBit{}, uses_accumulator = true },
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{ opname = .MOV, desc = "Register/memory to segment register", mask = 0b11111111, encoding = 0b10001110,
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has_segreg = true, has_address = true, word_size = None{} },
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{ opname = .MOV, desc = "Segment register to register/memory", mask = 0b11111111, encoding = 0b10001100,
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{ opname = .MOV, desc = "Segment register to register/memory", mask = 0b11111111, encoding = 0b10001100,
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has_segreg = true, has_address = true, word_size = None{} },
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{ opname = .TBD, desc = "Reg/memory with register to either", mask = 0b11000100, encoding = 0b00000000,
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{ opname = .PUSH, desc = "", mask = 0b11111111, encoding = 0b11111111,
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has_address = true, word_size = None{}, is_unary = true },
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{ opname = .PUSH, desc = "", mask = 0b11111000, encoding = 0b01010000,
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reg_info = reg_first_last, word_size = Force{}, is_unary = true },
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{ opname = .PUSH, desc = "", mask = 0b11100111, encoding = 0b00000110,
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has_segreg = true, reg_info = reg_first_middle, word_size = Force{}, is_unary = true },
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{ opname = .POP, desc = "", mask = 0b11111111, encoding = 0b10001111,
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has_address = true, word_size = None{}, is_unary = true },
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{ opname = .POP, desc = "", mask = 0b11111000, encoding = 0b01011000,
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reg_info = reg_first_last, word_size = Force{}, is_unary = true },
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{ opname = .POP, desc = "", mask = 0b11100111, encoding = 0b00000111,
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has_segreg = true, reg_info = reg_first_middle, word_size = None{}, is_unary = true },
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{ opname = .XCHG, desc = "", mask = 0b11111110, encoding = 0b10000110,
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reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true},
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{ opname = .XCHG, desc = "", mask = 0b11111000, encoding = 0b10010000,
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reg_info = reg_first_last, uses_accumulator = true, word_size = Force{}, },
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{ opname = .TBD, desc = "Reg/memory with register to either", mask = 0b11000100, encoding = 0b00000000,
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opcode_id = .First, reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true },
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{ opname = .TBD, desc = "Immediate to register/memory", mask = 0b11111100, encoding = 0b10000000,
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{ opname = .TBD, desc = "Immediate to register/memory", mask = 0b11111100, encoding = 0b10000000,
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opcode_id = .Second, has_data = true, has_address = true,
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word_size = LastBit{}, has_sign_extension = true },
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{ opname = .TBD, desc = "Immediate to accumulator", mask = 0b11000100, encoding = 0b00000100,
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@ -299,6 +317,8 @@ get_memory_type_string :: proc(mem_type: OperandType, is_word: bool) -> string {
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string_val = get_memory_string(val)
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case Accumulator:
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string_val = fmt.aprintf("[%d]", val)
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case SegmentRegister:
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string_val = segment_registers[val].fullname
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}
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return string_val
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}
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@ -383,13 +403,17 @@ main :: proc() {
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// asdf :u16 = 0b00000011_11101000
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// asdf2 :i16 = (i16)(asdf)
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// fmt.printfln("%d", asdf2)
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print_at_end := false
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read_next := false
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src_dst := true
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idx := 0
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added_label := false
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line_count := 0
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// last_opname: string
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last_opname: [3]byte
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instruction_builder := strings.builder_make()
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instruction_list := make([dynamic]string, 128)
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instruction_list := make([dynamic]string, 512)
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fmt.println("bits 16")
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for idx < bytes_read {
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processed := 1
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curr_byte := data[idx]
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@ -422,6 +446,7 @@ main :: proc() {
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switch val in instruction.word_size {
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case LastBit: is_word = curr_byte & 1 == 1
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case FourthBit: is_word = curr_byte & 0b0000_1000 != 0
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case Force: is_word = true
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case None:
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}
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@ -459,6 +484,10 @@ main :: proc() {
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} else if mod == 3 {
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lhs2 = (RegisterId)(registers[rm].code)
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}
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} else if instruction.has_segreg {
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lhs2 = (SegmentRegister)(segment_registers[reg].code)
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} else if instruction.uses_accumulator {
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lhs2 = (RegisterId)(registers[0].code)
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} else {
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lhs2 = (RegisterId)(registers[reg].code)
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}
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@ -470,9 +499,13 @@ main :: proc() {
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processed += word_signed ? 2 : 1
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rhs2 = (OperandType)(word_signed ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx]))
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has_immediate = true
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} else if instruction.has_accumulator {
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processed += is_word ? 2 : 1
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rhs2 = (OperandType)(is_word ? (Accumulator)(get_i16(data[data_idx:])) : (Accumulator)(data[data_idx]))
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} else if instruction.uses_accumulator {
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if _, ok := instruction.word_size.(LastBit); ok {
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processed += is_word ? 2 : 1
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rhs2 = (OperandType)(is_word ? (Accumulator)(get_i16(data[data_idx:])) : (Accumulator)(data[data_idx]))
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} else {
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rhs2 = (RegisterId)(reg)
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}
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} else {
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rhs2 = (RegisterId)(reg)
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}
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@ -500,6 +533,11 @@ main :: proc() {
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value := (i8)(data[idx+1]) + 2
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full_inst = fmt.aprintf("%s $%s%d ; %d", strings.to_lower(opname), value >= 0 ? "+" : "", value, value - 2)
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processed += 1
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} else if instruction.is_unary {
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if instruction.has_address {
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size_string = "word "
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}
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full_inst = fmt.aprintf("%s %s%s", opname, size_string, lhs)
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} else {
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opname = strings.to_lower(opname)
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if opname == "mov" {
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@ -512,13 +550,28 @@ main :: proc() {
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for i in 0..<processed {
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fmt.sbprintf(&instruction_builder, " %08b", data[idx + i])
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}
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instruction_list[line_count] = strings.clone(strings.to_string(instruction_builder))
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if print_at_end {
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instruction_list[line_count] = strings.clone(strings.to_string(instruction_builder))
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} else {
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op := strings.to_string(instruction_builder)
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if op[0:3] != string(last_opname[:]) {
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fmt.println()
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}
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copy(last_opname[:], op[0:3])
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fmt.println(op)
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}
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idx += processed
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line_count += 1
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strings.builder_reset(&instruction_builder)
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}
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fmt.println("bits 16\n")
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for i in 0..<line_count {
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fmt.println(instruction_list[i])
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if print_at_end {
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for i in 0..<line_count {
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opname := instruction_list[i]
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if !strings.has_prefix(opname, string(last_opname[:])) {
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fmt.println()
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}
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copy(last_opname[:], opname[0:3])
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fmt.println(instruction_list[i])
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}
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}
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}
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