Fix and simplify (delete) all the signage stuff
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ea7b65994b
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831a307975
@ -102,10 +102,13 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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op = MemoryAddr{ addr_id = rm }
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}
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} else if mod == 1 {
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op = MemoryAddr{ addr_id = rm , displacement_value = (i16)(data[2]) , displacement_size = .Signed8 }
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// NOTE: Per the 8086 manual in order to detect signed displacement, you have
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// to sign extend a byte to a word. In Odin like in other languages, first
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// cast to an i8, before casting to an i16 and it'll sign extend
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op = MemoryAddr{ addr_id = rm , displacement = i16(i8(data[2])) }
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processed^ += 1
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} else if mod == 2 {
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op = MemoryAddr{ addr_id = rm , displacement_value = get_i16(data[2:]) , displacement_size = .Signed16 }
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op = MemoryAddr{ addr_id = rm , displacement = get_i16(data[2:]) }
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processed^ += 2
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} else if mod == 3 {
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if word {
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@ -122,11 +125,8 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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word_signed &&= data[0] & 0b0000_0010 == 0
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}
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value: i16 = word_signed ? get_i16(data[data_idx:]) : i16(i8(data[data_idx]))
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operand = Immediate { value = value, size = word_signed ? .Signed16 : .Signed8 }
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operand = Immediate { value = value, size = word_signed ? ._16 : ._8 }
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processed^ += word_signed ? 2 : 1
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case .ImmediateUnsigned:
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operand = Immediate { value = i16(data[processed^]), size = .Unsigned8 }
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processed^ += 1
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case .Accumulator:
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operand = RegisterId { name = .ax, access = word ? .Full : .Low }
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case .DirectAddress:
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@ -148,7 +148,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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}
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case .ShiftRotate:
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v_flag := data[0] & 0b10 != 0
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operand = v_flag ? RegisterId { name = Register(1), access = .Low } : Immediate { value = 1 }
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operand = v_flag ? RegisterId { name = .cx, access = .Low } : Immediate { value = 1 }
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case .Repeat:
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bits := (data[1] & 0b1110) >> 1
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w := (data[1] & 0b1) == 1 ? "w" : "b"
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@ -164,7 +164,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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processed^ += 1
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case .DirectWithinSegment:
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value := (int)(get_i16(data[1:])) + total_bytes_processed + 3
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operand = Immediate { value = i16(value), size = .Signed16 }
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operand = Immediate { value = i16(value), size = ._16 }
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processed^ += 2
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case .Intersegment:
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operand = Intersegment {
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@ -5,6 +5,7 @@ import "core:fmt"
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import "core:math"
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import "core:strings"
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import "core:reflect"
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import "core:strconv"
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get_ip :: proc(cpu: ^Cpu) -> int { return int(cpu.registers[.ip].full) }
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@ -38,7 +39,7 @@ get_operand_value :: proc(cpu: ^Cpu, operand: Operand) -> i16 {
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value := i16(u16(cpu.memory[opr+1] << 8) | u16(cpu.memory[opr]))
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return value
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case MemoryAddr:
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idx := get_effective_address_value(cpu, opr.addr_id) + opr.displacement_value
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idx := get_effective_address_value(cpu, opr.addr_id) + opr.displacement
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value := i16(u16(cpu.memory[idx+1] << 8) | u16(cpu.memory[idx]))
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// fmt.println("Checking", idx)
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// for i in 0..<6 {
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@ -136,7 +137,7 @@ execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
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#partial switch inst.opname {
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case .MOV:
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if imm,ok := inst.src.(Immediate); ok {
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if imm.size == .Signed16 {
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if imm.size == ._16 {
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cpu.memory[addr] = u8(imm.value & 0x00FF)
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cpu.memory[addr+1] = u8((u16(imm.value) & 0xFF00) >> 8)
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} else {
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@ -150,7 +151,7 @@ execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
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value := get_operand_value(cpu, inst.src)
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effective_addr_val := get_effective_address_value(cpu, mem_addr.addr_id)
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addr := effective_addr_val + mem_addr.displacement_value
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addr := effective_addr_val + mem_addr.displacement
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cpu.memory[addr] = u8(value & 0x00FF)
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cpu.memory[addr+1] = u8((u16(value) & 0xFF00) >> 8)
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@ -39,7 +39,7 @@ calculate_effective_address :: proc(r_m: u8) -> string {
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get_memory_string :: proc(memoryAddr: MemoryAddr, has_segment: Maybe(RegisterId)) -> string {
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disp: string
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value := memoryAddr.displacement_value
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value := memoryAddr.displacement
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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@ -70,14 +70,7 @@ get_operand_string :: proc(operand: Operand, has_segment: Maybe(RegisterId)) ->
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case RegisterId:
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string_val = get_register_name(val)
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case Immediate:
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switch val.size {
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case .Signed8:
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string_val = fmt.aprintf("%d", i8(val.value))
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case .Unsigned8:
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string_val = fmt.aprintf("%d", u8(val.value))
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case .Signed16:
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string_val = fmt.aprintf("%d", i16(val.value))
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}
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case MemoryAddr:
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string_val = get_memory_string(val, has_segment)
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case DirectAddress:
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@ -131,15 +124,9 @@ get_instruction_string :: proc(inst_info: InstructionInfo, instruction: Instruct
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interseg_string = " far"
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}
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fmt.sbprintf(&instruction_builder, "%s%s %s%s", opname, interseg_string, size_string, src_str)
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} else {
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// note: i don't know why this is the case, but only the move has the word/byte
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// keyword next to the immediate, but other instructions have it on the memory address
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if opname == "mov" {
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fmt.sbprintf(&instruction_builder, "%s %s, %s%s", opname, dst_str, size_string, src_str)
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} else {
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fmt.sbprintf(&instruction_builder, "%s %s%s, %s", opname, size_string, dst_str, src_str)
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}
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}
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// Prepare padding and comment to add debug info
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b_len := strings.builder_len(instruction_builder)
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@ -6,6 +6,7 @@ import "core:fmt"
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import "core:math"
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import "core:strings"
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import "core:reflect"
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import "core:strconv"
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main :: proc() {
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f,err := os.open(os.args[1])
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@ -47,7 +48,12 @@ main :: proc() {
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memory = make([dynamic]u8, 1024 * 1024), // 1,048,576
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}
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num_idx := strings.last_index(os.args[1], "list-") + 5
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if listing_num,ok := strconv.parse_int(os.args[1][num_idx:num_idx+4]); ok {
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if listing_num > 42 {
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execute_instructions(&cpu, decoded_insts)
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}
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}
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if what_to_print == "registers" || what_to_print == "all" {
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fmt.println("Registers")
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@ -66,8 +72,9 @@ main :: proc() {
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failed_ref: bool
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path,ok := strings.replace(os.args[1], ".bin", ".txt", 1)
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ref_cpu,_ := extract_reference_cpu_state(path)
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ref_cpu,_ := parse_reference_cpu_state(path)
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for reg_val,name in ref_cpu.registers {
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if name == .ip && reg_val.full == 0 do continue
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if cpu.registers[name].full != reg_val.full {
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msg := "%s register does not match reference - Expected 0x%04x | Actual 0x%04x"
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fmt.printfln(msg, name, reg_val.full, cpu.registers[name].full)
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10
testing.odin
10
testing.odin
@ -7,7 +7,7 @@ import "core:strings"
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import "core:strconv"
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import "core:reflect"
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extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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parse_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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cpu: Cpu
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data,ok := os.read_entire_file(filename)
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@ -20,7 +20,6 @@ extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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lines := strings.split(content, "\n")
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defer delete(lines)
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ignore_ip_reg := true
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for line in lines {
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space_count := 0
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for c,i in line {
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@ -42,9 +41,6 @@ extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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}
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} else {
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reg_name := line[i:i+2]
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if reg_name == "ip" {
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ignore_ip_reg = false
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}
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reg_value := get_cpu_register_by_name(&cpu, reg_name)
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hex_string := line[i+6:i+10]
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if hex_num,ok := strconv.parse_int(hex_string, 16); ok {
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@ -56,9 +52,5 @@ extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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}
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}
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if ignore_ip_reg {
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cpu.registers[.ip] = cpu.registers[.ip]
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}
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return cpu, true
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}
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@ -58,9 +58,8 @@ RegisterId :: struct {
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access: RegisterAccess,
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}
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ImmediateSize :: enum {
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Signed8,
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Unsigned8,
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Signed16,
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_8,
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_16,
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}
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Immediate :: struct {
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value: i16,
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@ -68,8 +67,7 @@ Immediate :: struct {
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}
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MemoryAddr :: struct {
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addr_id: u8,
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displacement_value: i16,
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displacement_size: ImmediateSize,
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displacement: i16,
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}
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DirectAddress :: distinct i16
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Jump :: distinct i8
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@ -96,7 +94,6 @@ OperandInfo :: enum {
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SegmentRegister,
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RegisterMemory,
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Immediate,
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ImmediateUnsigned,
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Accumulator,
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DirectAddress,
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Jump,
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