Major refactor to define both operands so either can be empty
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.gitignore
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vendored
@ -3,3 +3,4 @@
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/asm_files/*.bin
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/8086_family_Users_Manual_1_.pdf
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/decoder8086
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/performance-aware
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611
decoder8086.odin
611
decoder8086.odin
@ -17,57 +17,6 @@ Register :: struct {
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code: u8,
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}
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OpName :: enum {
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TBD,
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MOV,
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PUSH,
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POP,
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XCHG,
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IN,
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OUT,
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XLAT,
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LEA,
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LDS,
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LES,
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ADD,
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ADC,
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SUB,
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CMP,
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JMP,
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JNZ,
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JNGE,
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JE,
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JZ,
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JL,
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JLE,
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JNG,
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JB,
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JNAE,
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JP,
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JPE,
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JNA,
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JBE,
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JO,
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JS,
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JNE,
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JNL,
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JGE,
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JNLE,
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JG,
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JNB,
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JAE,
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JNBE,
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JA,
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JNP,
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JPO,
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JNO,
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JNS,
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LOOP,
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LOOPZ,
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LOOPNZ,
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JCXZ,
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}
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registers := [8]Register {
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{fullname = "ax", bytename = "al", code = 0b000},
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{fullname = "cx", bytename = "cl", code = 0b001},
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@ -86,17 +35,13 @@ segment_registers := [4]Register {
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{fullname = "ds", code = 0b011},
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}
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variable_port := registers[2]
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RegInfo :: struct {
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in_first_byte: bool,
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shift_offset: u8,
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}
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OpCodeId :: enum {
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None,
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First,
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Second,
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}
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LastBit :: struct{}
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FourthBit :: struct{}
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Force :: struct{}
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@ -108,6 +53,15 @@ WordSize :: union {
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Force,
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}
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WordSize2 :: enum {
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None,
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LastBit,
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FourthBit,
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Always8,
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Always16,
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Unsigned8,
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}
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None :: struct {}
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Disp8 :: i8
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@ -145,15 +99,44 @@ MemoryAddr :: struct {
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addr_id: u8,
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displacement: Displacement
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}
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Accumulator :: distinct i16
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DirectAddress :: distinct i16
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SegmentRegister :: distinct i8
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OperandType :: union {
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Jump :: distinct i8
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VariablePort :: struct {}
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Repeat :: string
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Operand :: union {
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None,
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RegisterId,
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Immediate8,
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Immediate16,
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MemoryAddr,
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Accumulator,
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DirectAddress,
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SegmentRegister,
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Jump,
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VariablePort,
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Repeat,
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}
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OperandInfo :: enum {
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None,
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Register,
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SegmentRegister,
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RegisterMemory,
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Immediate,
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Accumulator,
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DirectAddress,
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Jump,
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VariablePort,
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ShiftRotate,
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Repeat,
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}
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RegisterEncodingBits :: enum {
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None,
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FirstByteLast3,
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SecondByteMiddle3,
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SecondByteLast3,
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FirstByteMiddle3,
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}
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InstructionInfo :: struct {
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@ -161,129 +144,17 @@ InstructionInfo :: struct {
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encoding: u8,
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opname: OpName,
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desc: string,
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opcode_id: OpCodeId,
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word_size: WordSize,
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reg_info: Maybe(RegInfo),
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has_data: bool,
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has_address: bool,
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uses_accumulator: bool,
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has_segreg: bool,
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src: OperandInfo,
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dst: OperandInfo,
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word_size: WordSize2,
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reg_info: RegisterEncodingBits,
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has_flip: bool,
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has_sign_extension: bool,
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is_jump: bool,
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is_unary: bool,
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check_second_encoding: bool,
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consume_extra_bytes: int,
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shift_rotate_flag: bool,
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}
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// TODO: Maybe we can get rid of it since I don't have to specify the shift_offset,
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// not like it changes a lot
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reg_first_last := RegInfo{ in_first_byte = true, shift_offset = 0 }
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reg_second_middle := RegInfo{ in_first_byte = false, shift_offset = 3 }
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reg_first_middle := RegInfo{ in_first_byte = true, shift_offset = 3 }
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instructions := [?]InstructionInfo {
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{ opname = .MOV, desc = "Register/memory to/from register", mask = 0b11111100, encoding = 0b10001000,
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reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true },
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{ opname = .MOV, desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b11000110,
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has_data = true, has_address = true, word_size = LastBit{}, },
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{ opname = .MOV, desc = "Immediate to register", mask = 0b11110000, encoding = 0b10110000,
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reg_info = reg_first_last, has_data = true, word_size = FourthBit{} },
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{ opname = .MOV, desc = "Memory to accumulator", mask = 0b11111110, encoding = 0b10100000,
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has_flip = true, word_size = LastBit{}, uses_accumulator = true },
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{ opname = .MOV, desc = "Accumulator to memory", mask = 0b11111110, encoding = 0b10100010,
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has_flip = true, word_size = LastBit{}, uses_accumulator = true },
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{ opname = .MOV, desc = "Register/memory to segment register", mask = 0b11111111, encoding = 0b10001110,
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has_segreg = true, has_address = true, word_size = None{} },
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{ opname = .MOV, desc = "Segment register to register/memory", mask = 0b11111111, encoding = 0b10001100,
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has_segreg = true, has_address = true, word_size = None{} },
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{ opname = .PUSH, desc = "", mask = 0b11111111, encoding = 0b11111111,
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has_address = true, word_size = None{}, is_unary = true },
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{ opname = .PUSH, desc = "", mask = 0b11111000, encoding = 0b01010000,
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reg_info = reg_first_last, word_size = Force{}, is_unary = true },
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{ opname = .PUSH, desc = "", mask = 0b11100111, encoding = 0b00000110,
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has_segreg = true, reg_info = reg_first_middle, word_size = Force{}, is_unary = true },
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{ opname = .POP, desc = "", mask = 0b11111111, encoding = 0b10001111,
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has_address = true, word_size = None{}, is_unary = true },
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{ opname = .POP, desc = "", mask = 0b11111000, encoding = 0b01011000,
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reg_info = reg_first_last, word_size = Force{}, is_unary = true },
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{ opname = .POP, desc = "", mask = 0b11100111, encoding = 0b00000111,
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has_segreg = true, reg_info = reg_first_middle, word_size = None{}, is_unary = true },
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{ opname = .XCHG, desc = "", mask = 0b11111110, encoding = 0b10000110,
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reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true},
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{ opname = .XCHG, desc = "", mask = 0b11111000, encoding = 0b10010000,
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reg_info = reg_first_last, uses_accumulator = true, word_size = Force{}, },
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{ opname = .IN, desc = "", mask = 0b11111110, encoding = 0b11100100,
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has_data = true, word_size = LastBit{}, },
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{ opname = .IN, desc = "", mask = 0b11111110, encoding = 0b11101100,
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word_size = LastBit{}, },
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{ opname = .OUT, desc = "", mask = 0b11111110, encoding = 0b11100110,
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has_data = true, word_size = FourthBit{}, },
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{ opname = .OUT, desc = "", mask = 0b11111110, encoding = 0b11101110,
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word_size = LastBit{}, },
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{ opname = .XLAT, desc = "", mask = 0b11111111, encoding = 0b11010111,
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},
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{ opname = .LEA, desc = "", mask = 0b11111111, encoding = 0b10001101,
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has_address = true },
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{ opname = .LDS, desc = "", mask = 0b11111111, encoding = 0b11000101,
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has_address = true },
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{ opname = .LES, desc = "", mask = 0b11111111, encoding = 0b11000100,
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has_address = true },
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{ opname = .TBD, desc = "Reg/memory with register to either", mask = 0b11000100, encoding = 0b00000000,
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opcode_id = .First, reg_info = reg_second_middle, has_address = true, word_size = LastBit{}, has_flip = true },
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{ opname = .TBD, desc = "Immediate to register/memory", mask = 0b11111100, encoding = 0b10000000,
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opcode_id = .Second, has_data = true, has_address = true,
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word_size = LastBit{}, has_sign_extension = true },
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{ opname = .TBD, desc = "Immediate to accumulator", mask = 0b11000100, encoding = 0b00000100,
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word_size = LastBit{}, has_data = true },
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{ opname = .JE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110100, is_jump = true},
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{ opname = .JZ, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110100, is_jump = true},
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{ opname = .JL, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111100, is_jump = true},
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{ opname = .JNGE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111100, is_jump = true},
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{ opname = .JLE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111110, is_jump = true},
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{ opname = .JNG, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111110, is_jump = true},
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{ opname = .JB, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110010, is_jump = true},
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{ opname = .JNAE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110010, is_jump = true},
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{ opname = .JBE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110110, is_jump = true},
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{ opname = .JNA, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110110, is_jump = true},
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{ opname = .JP, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111010, is_jump = true},
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{ opname = .JPE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111010, is_jump = true},
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{ opname = .JO, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110000, is_jump = true},
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{ opname = .JS, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111000, is_jump = true},
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{ opname = .JNE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110101, is_jump = true},
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{ opname = .JNZ, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110101, is_jump = true},
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{ opname = .JNL, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111101, is_jump = true},
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{ opname = .JGE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111101, is_jump = true},
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{ opname = .JNLE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111111, is_jump = true},
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{ opname = .JG, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111111, is_jump = true},
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{ opname = .JNB, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110011, is_jump = true},
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{ opname = .JAE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110011, is_jump = true},
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{ opname = .JNBE, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110111, is_jump = true},
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{ opname = .JA, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110111, is_jump = true},
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{ opname = .JNP, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111011, is_jump = true},
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{ opname = .JPO, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111011, is_jump = true},
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{ opname = .JNO, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01110001, is_jump = true},
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{ opname = .JNS, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b01111001, is_jump = true},
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{ opname = .LOOP, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b11100010, is_jump = true},
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{ opname = .LOOPZ, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b11100001, is_jump = true},
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{ opname = .LOOPNZ, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b11100000, is_jump = true},
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{ opname = .JCXZ, desc = "Jump on not zero", mask = 0b11111111, encoding = 0b11100011, is_jump = true},
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}
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inst_map := make(map[u8]InstructionInfo)
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RIGHT_ALIGN_AMOUNT := 35
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calculate_effective_address :: proc(r_m: u8) -> string {
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@ -327,9 +198,11 @@ get_memory_string :: proc(memoryAddr: MemoryAddr) -> string {
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return text
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}
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get_memory_type_string :: proc(mem_type: OperandType, is_word: bool) -> string {
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get_operand_string :: proc(operand: Operand, is_word: bool) -> string {
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string_val: string
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switch val in mem_type {
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switch val in operand {
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case None:
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string_val = ""
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case RegisterId:
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string_val = is_word ? registers[val].fullname : registers[val].bytename
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case Immediate8:
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@ -338,10 +211,16 @@ get_memory_type_string :: proc(mem_type: OperandType, is_word: bool) -> string {
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string_val = fmt.aprintf("%d", val)
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case MemoryAddr:
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string_val = get_memory_string(val)
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case Accumulator:
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case DirectAddress:
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string_val = fmt.aprintf("[%d]", val)
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case SegmentRegister:
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string_val = segment_registers[val].fullname
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case Jump:
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string_val = fmt.aprintf("$%s%d", val >= 0 ? "+" : "", val)
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case VariablePort:
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string_val = variable_port.fullname
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case Repeat:
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string_val = (string)(val)
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}
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return string_val
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}
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@ -380,9 +259,22 @@ get_displacement_string :: proc(displacement: Displacement) -> string {
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return disp
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}
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get_repeat_op :: proc(data: u8) -> Repeat {
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bits := (data & 0b1110) >> 1
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w := (data & 0b1) == 1 ? "w" : "b"
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rep: string
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switch bits {
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case 0b010: rep = "movs"
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case 0b011: rep = "cmps"
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case 0b101: rep = "stos"
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case 0b110: rep = "lods"
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case 0b111: rep = "scas"
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}
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return Repeat(fmt.aprintf("%s%s", rep, w))
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}
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try_find_instruction :: proc(b: u8) -> (InstructionInfo, bool) {
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for inst in instructions {
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// fmt.print(inst.encoding, ",")
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if inst.encoding == (b & inst.mask) {
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return inst, true
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}
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@ -390,19 +282,149 @@ try_find_instruction :: proc(b: u8) -> (InstructionInfo, bool) {
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return InstructionInfo{}, false
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}
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get_opname :: proc(b: u8) -> string {
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get_opname :: proc(opname: OpName, data: []u8) -> string {
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name: string
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switch b & 0b00111000 >> 3 {
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case 0b000: name = "add"
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case 0b010: name = "adc"
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case 0b101: name = "sub"
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case 0b111: name = "cmp"
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if opname == .TBD2 {
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switch data[1] & 0b00111000 >> 3 {
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case 0b000: name = "inc"
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case 0b001: name = "dec"
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case 0b010: name = "call"
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case 0b011: name = "call"
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case 0b100: name = "jmp"
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case 0b101: name = "jmp"
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case 0b110: name = "push"
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}
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} else if opname == .TBD5 {
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switch data[1] & 0b00111000 >> 3 {
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case 0b000: name = "test"
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case 0b001: name = "dec"
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case 0b010: name = "not"
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case 0b011: name = "neg"
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case 0b100: name = "mul"
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case 0b101: name = "imul"
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case 0b110: name = "div"
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case 0b111: name = "idiv"
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}
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} else if opname == .TBD6 {
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switch data[1] & 0b00111000 >> 3 {
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case 0b000: name = "rol"
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case 0b001: name = "ror"
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case 0b010: name = "rcl"
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case 0b011: name = "rcr"
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case 0b100: name = "shl"
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case 0b101: name = "shr"
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case 0b111: name = "sar"
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}
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} else {
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bits: u8
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if opname == .TBD1 || opname == .TBD3 {
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bits = data[0] & 0b00111000 >> 3
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} else {
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bits = data[1] & 0b00111000 >> 3
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}
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switch bits {
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case 0b000: name = "add"
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case 0b001: name = "or"
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case 0b010: name = "adc"
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case 0b011: name = "sbb"
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case 0b100: name = "and"
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case 0b101: name = "sub"
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case 0b110: name = "xor"
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case 0b111: name = "cmp"
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}
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}
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return name
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}
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parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, processed: ^int, word: bool) -> Operand {
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operand: Operand = None{}
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switch opinfo {
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case .None:
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case .Register:
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// rm: u8 = data[1] & 0b111
|
||||
// dst_opr = (RegisterId)(registers[rm].code)
|
||||
reg: u8
|
||||
// Read the RegisterEncodingBits
|
||||
switch inst.reg_info {
|
||||
case .None:
|
||||
// panic("Register is required but the encoded location is not provided")
|
||||
case .FirstByteLast3:
|
||||
reg = data[0] & 0b111
|
||||
case .FirstByteMiddle3:
|
||||
reg = (data[0] >> 3) & 0b111
|
||||
case .SecondByteMiddle3:
|
||||
reg = (data[1] >> 3) & 0b111
|
||||
case .SecondByteLast3:
|
||||
reg = data[1] & 0b111
|
||||
}
|
||||
operand = (RegisterId)(registers[reg].code)
|
||||
case .SegmentRegister:
|
||||
reg: u8
|
||||
switch inst.reg_info {
|
||||
case .None:
|
||||
// panic("Register is required but the encoded location is not provided")
|
||||
case .FirstByteLast3:
|
||||
reg = data[0] & 0b111
|
||||
case .FirstByteMiddle3:
|
||||
reg = (data[0] >> 3) & 0b111
|
||||
case .SecondByteMiddle3:
|
||||
reg = (data[1] >> 3) & 0b111
|
||||
case .SecondByteLast3:
|
||||
reg = data[1] & 0b111
|
||||
}
|
||||
operand = (SegmentRegister)(segment_registers[reg].code)
|
||||
case .RegisterMemory:
|
||||
mod := data[1] >> 6
|
||||
rm := data[1] & 0b111
|
||||
processed^ += 1
|
||||
op: Operand
|
||||
if mod == 0 {
|
||||
if rm == 0b110 {
|
||||
op = (DirectAddress)(get_i16(data[2:]))
|
||||
processed^ += 2
|
||||
} else {
|
||||
op = MemoryAddr{ addr_id = rm , displacement = None{} }
|
||||
}
|
||||
} else if mod == 1 {
|
||||
op = MemoryAddr{ addr_id = rm , displacement = (i8)(data[2]) }
|
||||
processed^ += 1
|
||||
} else if mod == 2 {
|
||||
op = MemoryAddr{ addr_id = rm , displacement = get_i16(data[2:]) }
|
||||
processed^ += 2
|
||||
} else if mod == 3 {
|
||||
op = (RegisterId)(registers[rm].code)
|
||||
}
|
||||
operand = op
|
||||
case .Immediate:
|
||||
data_idx := processed^
|
||||
word_signed := word
|
||||
if inst.has_sign_extension {
|
||||
word_signed &&= data[0] & 0b0000_0010 == 0
|
||||
}
|
||||
operand = (Operand)(word_signed ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx]))
|
||||
processed^ += word_signed ? 2 : 1
|
||||
case .Accumulator:
|
||||
operand = (RegisterId)(registers[0].code)
|
||||
case .DirectAddress:
|
||||
operand = (DirectAddress)(get_i16(data[1:]))
|
||||
processed^ += 2
|
||||
case .Jump:
|
||||
processed^ += 1
|
||||
// NOTE: In order to mimic the label offset, you have to take the value you got and add two
|
||||
operand = (Jump)((i8)(data[1]) + 2)
|
||||
case .VariablePort:
|
||||
operand = VariablePort{}
|
||||
case .ShiftRotate:
|
||||
v_flag := data[0] & 0b10 != 0
|
||||
operand = v_flag ? (RegisterId)(registers[1].code) : (Immediate8)(1)
|
||||
case .Repeat:
|
||||
operand = get_repeat_op(data[1])
|
||||
processed^ += 1
|
||||
}
|
||||
return operand
|
||||
}
|
||||
|
||||
main :: proc() {
|
||||
// f,err := os.open(len(os.args) > 1 ? os.args[1] : "./asm_files/01-02-39.bin")
|
||||
f,err := os.open(os.args[1])
|
||||
if err != os.ERROR_NONE {
|
||||
fmt.eprintln("ERROR:", err)
|
||||
@ -417,10 +439,6 @@ main :: proc() {
|
||||
os.exit(1)
|
||||
}
|
||||
|
||||
for inst in instructions {
|
||||
inst_map[inst.encoding] = inst
|
||||
}
|
||||
|
||||
if false {
|
||||
os.exit(0)
|
||||
}
|
||||
@ -433,8 +451,10 @@ main :: proc() {
|
||||
idx := 0
|
||||
added_label := false
|
||||
line_count := 0
|
||||
// last_opname: string
|
||||
has_lock: bool
|
||||
has_segment: bool
|
||||
last_opname: [3]byte
|
||||
repeating_op_count := 0
|
||||
instruction_builder := strings.builder_make()
|
||||
instruction_list := make([dynamic]string, 512)
|
||||
fmt.println("bits 16")
|
||||
@ -442,150 +462,121 @@ main :: proc() {
|
||||
processed := 1
|
||||
curr_byte := data[idx]
|
||||
|
||||
instruction, ok := try_find_instruction(curr_byte)
|
||||
inst, ok := try_find_instruction(curr_byte)
|
||||
if !ok {
|
||||
txt := "unknown instruction"
|
||||
line := fmt.aprintf("%s %*[1]s %8b", txt, RIGHT_ALIGN_AMOUNT - len(txt), ";;", curr_byte)
|
||||
instruction_list[line_count] = line
|
||||
line_count += 1
|
||||
if print_at_end {
|
||||
line := fmt.aprintf("%s %*[1]s %8b", txt, RIGHT_ALIGN_AMOUNT - len(txt), ";;", curr_byte)
|
||||
instruction_list[line_count] = line
|
||||
line_count += 1
|
||||
} else {
|
||||
fmt.printfln("%s %*[1]s %8b", txt, RIGHT_ALIGN_AMOUNT - len(txt), ";;", curr_byte)
|
||||
}
|
||||
idx += 1
|
||||
continue
|
||||
}
|
||||
|
||||
lhs2: OperandType
|
||||
rhs2: OperandType
|
||||
is_word: bool
|
||||
is_immediate := false
|
||||
flip_dst := false
|
||||
has_memory_addr := false
|
||||
has_immediate := false
|
||||
rm: u8
|
||||
mod: u8
|
||||
reg: u8
|
||||
// Here we check if the instruction affects the next instruction
|
||||
if inst.opname == .LOCK {
|
||||
has_lock = true
|
||||
idx += 1
|
||||
continue
|
||||
} else if inst.opname == .SEGMENT {
|
||||
has_segment = true
|
||||
idx += 1
|
||||
continue
|
||||
}
|
||||
has_segment = false
|
||||
|
||||
if instruction.has_flip {
|
||||
flip_dst = curr_byte & 2 != 0
|
||||
src_opr: Operand
|
||||
dst_opr: Operand
|
||||
|
||||
word: bool
|
||||
flip: bool
|
||||
op: Operand
|
||||
|
||||
if inst.has_flip {
|
||||
flip = curr_byte & 2 != 0
|
||||
}
|
||||
|
||||
switch val in instruction.word_size {
|
||||
case LastBit: is_word = curr_byte & 1 == 1
|
||||
case FourthBit: is_word = curr_byte & 0b0000_1000 != 0
|
||||
case Force: is_word = true
|
||||
case None:
|
||||
#partial switch inst.word_size {
|
||||
case .LastBit: word = curr_byte & 1 == 1
|
||||
case .FourthBit: word = curr_byte & 0b0000_1000 != 0
|
||||
case .Always16: word = true
|
||||
}
|
||||
|
||||
if reg_info, ok := instruction.reg_info.(RegInfo); ok {
|
||||
b := reg_info.in_first_byte ? data[idx] : data[idx+1]
|
||||
reg = (b >> reg_info.shift_offset) & 0b111
|
||||
}
|
||||
|
||||
|
||||
data_idx := idx + 1
|
||||
|
||||
if instruction.has_address {
|
||||
mod = data[idx+1] >> 6
|
||||
rm = data[idx+1] & 0b00000111
|
||||
|
||||
data_idx += 1 + ((int)(mod) % 3)
|
||||
processed += 1 + ((int)(mod) % 3)
|
||||
|
||||
if mod == 0 {
|
||||
if rm == 0b110 {
|
||||
lhs2 = (Accumulator)(get_i16(data[idx+2:]))
|
||||
processed += 2
|
||||
data_idx += 2
|
||||
} else {
|
||||
lhs2 = MemoryAddr{ addr_id = rm , displacement = None{} }
|
||||
}
|
||||
// NOTE: This also works when it's an Accumulator apparently
|
||||
has_memory_addr = true
|
||||
} else if mod == 1 {
|
||||
lhs2 = MemoryAddr{ addr_id = rm , displacement = (i8)(data[idx+2]) }
|
||||
has_memory_addr = true
|
||||
} else if mod == 2 {
|
||||
lhs2 = MemoryAddr{ addr_id = rm , displacement = get_i16(data[idx+2:]) }
|
||||
has_memory_addr = true
|
||||
} else if mod == 3 {
|
||||
lhs2 = (RegisterId)(registers[rm].code)
|
||||
}
|
||||
} else if instruction.has_segreg {
|
||||
lhs2 = (SegmentRegister)(segment_registers[reg].code)
|
||||
} else if instruction.uses_accumulator {
|
||||
lhs2 = (RegisterId)(registers[0].code)
|
||||
} else {
|
||||
lhs2 = (RegisterId)(registers[reg].code)
|
||||
}
|
||||
if instruction.has_data {
|
||||
word_signed := is_word
|
||||
if instruction.has_sign_extension {
|
||||
word_signed = is_word && curr_byte & 0b0000_0010 == 0
|
||||
}
|
||||
processed += word_signed ? 2 : 1
|
||||
rhs2 = (OperandType)(word_signed ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx]))
|
||||
has_immediate = true
|
||||
} else if instruction.uses_accumulator {
|
||||
if _, ok := instruction.word_size.(LastBit); ok {
|
||||
processed += is_word ? 2 : 1
|
||||
rhs2 = (OperandType)(is_word ? (Accumulator)(get_i16(data[data_idx:])) : (Accumulator)(data[data_idx]))
|
||||
} else {
|
||||
rhs2 = (RegisterId)(reg)
|
||||
}
|
||||
} else {
|
||||
rhs2 = (RegisterId)(reg)
|
||||
}
|
||||
|
||||
if flip_dst {
|
||||
lhs2, rhs2 = rhs2, lhs2
|
||||
}
|
||||
|
||||
lhs := get_memory_type_string(lhs2, is_word)
|
||||
rhs := get_memory_type_string(rhs2, is_word)
|
||||
size_string := has_immediate && has_memory_addr ? is_word ? "word " : "byte " : ""
|
||||
full_inst: string
|
||||
opname: string
|
||||
if instruction.opname == .TBD {
|
||||
if instruction.opcode_id == .Second {
|
||||
opname = strings.to_lower(fmt.aprintf("%s", get_opname(data[idx+1])))
|
||||
} else {
|
||||
opname = strings.to_lower(fmt.aprintf("%s", get_opname(curr_byte)))
|
||||
// TODO: Figure out a way to do this in the string builder
|
||||
if inst.check_second_encoding {
|
||||
opname = strings.to_lower(fmt.aprintf("%s", get_opname(inst.opname, data[idx:])))
|
||||
// NOTE: This is a special case because it matches the bit pattern of .TBD5,
|
||||
// but the instruction itself is different
|
||||
if opname == "not" {
|
||||
inst = not_inst
|
||||
}
|
||||
} else {
|
||||
opname = strings.to_lower(fmt.aprintf("%s", instruction.opname))
|
||||
opname = strings.to_lower(fmt.aprintf("%s", inst.opname))
|
||||
}
|
||||
if instruction.is_jump {
|
||||
// NOTE: In order to mimic the label offset, you have to take the value you got and add two
|
||||
value := (i8)(data[idx+1]) + 2
|
||||
full_inst = fmt.aprintf("%s $%s%d ; %d", strings.to_lower(opname), value >= 0 ? "+" : "", value, value - 2)
|
||||
processed += 1
|
||||
} else if instruction.is_unary {
|
||||
if instruction.has_address {
|
||||
size_string = "word "
|
||||
|
||||
dst_opr = parse_operand(inst, inst.dst, data[idx:], &processed, word)
|
||||
src_opr = parse_operand(inst, inst.src, data[idx:], &processed, word)
|
||||
|
||||
// TODO: This is ugly as hell
|
||||
_,ok_1 := src_opr.(Immediate8)
|
||||
_,ok_2 := src_opr.(Immediate16)
|
||||
_,ok_3 := dst_opr.(MemoryAddr);
|
||||
_,ok_4 := dst_opr.(DirectAddress);
|
||||
shiftrot := inst.src == .ShiftRotate
|
||||
size_string := ""
|
||||
if ((ok_1 || ok_2) && (ok_3 || ok_4)) || ((ok_3 || ok_4) && shiftrot) {
|
||||
size_string = word ? "word " : "byte "
|
||||
}
|
||||
|
||||
if flip {
|
||||
src_opr, dst_opr = dst_opr, src_opr
|
||||
}
|
||||
|
||||
dst_str := get_operand_string(dst_opr, word)
|
||||
src_str := get_operand_string(src_opr, word)
|
||||
full_inst: string
|
||||
if dst_str == "" {
|
||||
_,ok_1 := src_opr.(MemoryAddr);
|
||||
_,ok_2 := src_opr.(DirectAddress);
|
||||
if (ok_1 || ok_2) && inst.word_size != .Always16 {
|
||||
size_string = word ? "word " : "byte "
|
||||
}
|
||||
full_inst = fmt.aprintf("%s %s%s", opname, size_string, lhs)
|
||||
full_inst = fmt.aprintf("%s %s%s", opname, size_string, src_str)
|
||||
} else {
|
||||
opname = strings.to_lower(opname)
|
||||
// NOTE: I don't know why this is the case, but only the move has the word/byte
|
||||
// keyword next to the immediate, but other instructions have it on the memory address
|
||||
if opname == "mov" {
|
||||
full_inst = fmt.aprintf("%s %s, %s%s", opname, lhs, size_string, rhs)
|
||||
full_inst = fmt.aprintf("%s %s, %s%s", opname, dst_str, size_string, src_str)
|
||||
} else {
|
||||
full_inst = fmt.aprintf("%s %s%s, %s", opname, size_string, lhs, rhs)
|
||||
full_inst = fmt.aprintf("%s %s%s, %s", opname, size_string, dst_str, src_str)
|
||||
}
|
||||
}
|
||||
|
||||
processed += inst.consume_extra_bytes
|
||||
|
||||
// fmt.sbprintf(&instruction_builder, "%s%s%s %*[2]s", lock_string, seg_string, full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;")
|
||||
fmt.sbprintf(&instruction_builder, "%s %*[1]s", full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;")
|
||||
for i in 0..<processed {
|
||||
fmt.sbprintf(&instruction_builder, " %08b", data[idx + i])
|
||||
}
|
||||
if print_at_end {
|
||||
instruction_list[line_count] = strings.clone(strings.to_string(instruction_builder))
|
||||
} else {
|
||||
op := strings.to_string(instruction_builder)
|
||||
if op[0:3] != string(last_opname[:]) {
|
||||
|
||||
op2 := strings.to_string(instruction_builder)
|
||||
if op2[0:3] != string(last_opname[:]) {
|
||||
if repeating_op_count > 1 {
|
||||
fmt.println()
|
||||
}
|
||||
copy(last_opname[:], op[0:3])
|
||||
fmt.println(op)
|
||||
repeating_op_count = 0
|
||||
} else {
|
||||
repeating_op_count += 1
|
||||
}
|
||||
copy(last_opname[:], op2[0:3])
|
||||
fmt.println(op2)
|
||||
|
||||
idx += processed
|
||||
line_count += 1
|
||||
strings.builder_reset(&instruction_builder)
|
||||
}
|
||||
if print_at_end {
|
||||
|
||||
277
instructions.odin
Normal file
277
instructions.odin
Normal file
@ -0,0 +1,277 @@
|
||||
package decoder_8086
|
||||
|
||||
OpName :: enum {
|
||||
TBD1,
|
||||
TBD2,
|
||||
TBD3,
|
||||
TBD4,
|
||||
TBD5,
|
||||
TBD6,
|
||||
MOV,
|
||||
PUSH,
|
||||
POP,
|
||||
XCHG,
|
||||
IN,
|
||||
OUT,
|
||||
XLAT,
|
||||
LEA,
|
||||
LDS,
|
||||
LES,
|
||||
LAHF,
|
||||
SAHF,
|
||||
PUSHF,
|
||||
POPF,
|
||||
ADD,
|
||||
ADC,
|
||||
INC,
|
||||
AAA,
|
||||
DAA,
|
||||
SUB,
|
||||
SBB,
|
||||
DEC,
|
||||
NEG,
|
||||
CMP,
|
||||
AAS,
|
||||
DAS,
|
||||
AAM,
|
||||
DIV,
|
||||
IDIV,
|
||||
AAD,
|
||||
CBW,
|
||||
CWD,
|
||||
NOT,
|
||||
TEST,
|
||||
REP,
|
||||
RET,
|
||||
INT,
|
||||
INT3,
|
||||
INTO,
|
||||
IRET,
|
||||
CLC,
|
||||
CMC,
|
||||
STC,
|
||||
CLD,
|
||||
STD,
|
||||
CLI,
|
||||
STI,
|
||||
HLT,
|
||||
WAIT,
|
||||
ESC,
|
||||
LOCK,
|
||||
SEGMENT,
|
||||
JMP,
|
||||
JNZ,
|
||||
JNGE,
|
||||
JE,
|
||||
JZ,
|
||||
JL,
|
||||
JLE,
|
||||
JNG,
|
||||
JB,
|
||||
JNAE,
|
||||
JP,
|
||||
JPE,
|
||||
JNA,
|
||||
JBE,
|
||||
JO,
|
||||
JS,
|
||||
JNE,
|
||||
JNL,
|
||||
JGE,
|
||||
JNLE,
|
||||
JG,
|
||||
JNB,
|
||||
JAE,
|
||||
JNBE,
|
||||
JA,
|
||||
JNP,
|
||||
JPO,
|
||||
JNO,
|
||||
JNS,
|
||||
LOOP,
|
||||
LOOPZ,
|
||||
LOOPNZ,
|
||||
JCXZ,
|
||||
}
|
||||
|
||||
not_inst := InstructionInfo {
|
||||
opname = .NOT, desc = "", mask = 0b11111110, encoding = 0b11110110,
|
||||
src = .RegisterMemory, word_size = .LastBit
|
||||
}
|
||||
|
||||
|
||||
instructions := [?]InstructionInfo {
|
||||
{ opname = .TBD1, desc = "Immediate to accumulator",
|
||||
mask = 0b11000110, encoding = 0b00000100, check_second_encoding = true,
|
||||
dst = .Accumulator, src = .Immediate,
|
||||
word_size = .LastBit, },
|
||||
{ opname = .TBD2, desc = "", check_second_encoding = true,
|
||||
mask = 0b11111110, encoding = 0b11111110,
|
||||
src = .RegisterMemory,
|
||||
word_size = .LastBit, },
|
||||
{ opname = .TBD3, desc = "", check_second_encoding = true,
|
||||
mask = 0b11000100, encoding = 0b00000000,
|
||||
dst = .RegisterMemory, src = .Register,
|
||||
word_size = .LastBit, reg_info = .SecondByteMiddle3, has_flip = true },
|
||||
{ opname = .TBD4, desc = "", check_second_encoding = true,
|
||||
mask = 0b11111100, encoding = 0b10000000,
|
||||
dst = .RegisterMemory, src = .Immediate,
|
||||
word_size = .LastBit, has_sign_extension = true },
|
||||
{ opname = .TBD5, desc = "", check_second_encoding = true,
|
||||
mask = 0b11111110, encoding = 0b11110110,
|
||||
dst = .Immediate, src = .RegisterMemory, word_size = .LastBit, },
|
||||
{ opname = .TBD6, desc = "", check_second_encoding = true,
|
||||
mask = 0b11111100, encoding = 0b11010000,
|
||||
dst = .RegisterMemory, src = .ShiftRotate, word_size = .LastBit, },
|
||||
{ opname = .MOV, desc = "Register/memory to/from register",
|
||||
mask = 0b11111100, encoding = 0b10001000,
|
||||
dst = .RegisterMemory, src = .Register,
|
||||
word_size = .LastBit, reg_info = .SecondByteMiddle3, has_flip = true },
|
||||
{ opname = .MOV, desc = "Immediate to register/memory",
|
||||
mask = 0b11111110, encoding = 0b11000110,
|
||||
dst = .RegisterMemory, src = .Immediate,
|
||||
word_size = .LastBit, },
|
||||
{ opname = .MOV, desc = "Immediate to register",
|
||||
mask = 0b11110000, encoding = 0b10110000,
|
||||
dst = .Register, src = .Immediate,
|
||||
word_size = .FourthBit, reg_info = .FirstByteLast3 },
|
||||
{ opname = .MOV, desc = "Memory to accumulator",
|
||||
mask = 0b11111110, encoding = 0b10100000,
|
||||
dst = .Accumulator, src = .DirectAddress,
|
||||
word_size = .LastBit, },
|
||||
{ opname = .MOV, desc = "Accumulator to memory",
|
||||
mask = 0b11111110, encoding = 0b10100010,
|
||||
dst = .DirectAddress, src = .Accumulator,
|
||||
word_size = .LastBit, },
|
||||
{ opname = .PUSH, desc = "", mask = 0b11111000, encoding = 0b01010000,
|
||||
src = .Register, reg_info = .FirstByteLast3,
|
||||
word_size = .Always16, },
|
||||
{ opname = .PUSH, desc = "", mask = 0b11100111, encoding = 0b00000110,
|
||||
src = .SegmentRegister, reg_info = .FirstByteMiddle3,
|
||||
word_size = .Always16, },
|
||||
{ opname = .POP, desc = "", mask = 0b11111111, encoding = 0b10001111,
|
||||
src = .RegisterMemory,},
|
||||
{ opname = .POP, desc = "", mask = 0b11111000, encoding = 0b01011000,
|
||||
src = .Register, reg_info = .FirstByteLast3,
|
||||
word_size = .Always16, },
|
||||
{ opname = .POP, desc = "", mask = 0b11100111, encoding = 0b00000111,
|
||||
src = .SegmentRegister, reg_info = .FirstByteMiddle3,
|
||||
word_size = .Always16, },
|
||||
{ opname = .XCHG, desc = "", mask = 0b11111110, encoding = 0b10000110,
|
||||
dst = .RegisterMemory, src = .Register,
|
||||
reg_info = .SecondByteMiddle3, has_flip = true },
|
||||
{ opname = .XCHG, desc = "", mask = 0b11111000, encoding = 0b10010000,
|
||||
dst = .Accumulator, src = .Register,
|
||||
reg_info = .FirstByteLast3, has_flip = true, word_size = .Always16 },
|
||||
{ opname = .IN, desc = "", mask = 0b11111110, encoding = 0b11100100,
|
||||
dst = .Accumulator, src = .Immediate,
|
||||
// TODO: Everything works just fine, but the problem here is that if you want it to
|
||||
// show up as an unsigned int, then we have to change the types because the number
|
||||
// 200, for instance, will show up as a negative, we would have to create an unsigned
|
||||
// variant of the Immediate value. Maybe we can have the value and the sign as a struct
|
||||
word_size = .Unsigned8, },
|
||||
{ opname = .IN, desc = "", mask = 0b11111110, encoding = 0b11101100,
|
||||
dst = .Accumulator, src = .VariablePort,
|
||||
word_size = .LastBit, },
|
||||
{ opname = .OUT, desc = "", mask = 0b11111110, encoding = 0b11100110,
|
||||
dst = .Immediate, src = .Accumulator,
|
||||
word_size = .Unsigned8, },
|
||||
{ opname = .OUT, desc = "", mask = 0b11111110, encoding = 0b11101110,
|
||||
dst = .VariablePort, src = .Accumulator,
|
||||
word_size = .LastBit, },
|
||||
{ opname = .XLAT, desc = "", mask = 0b11111111, encoding = 0b11010111,},
|
||||
{ opname = .LEA, desc = "", mask = 0b11111111, encoding = 0b10001101,
|
||||
dst = .Register, src = .RegisterMemory,
|
||||
reg_info = .SecondByteMiddle3, word_size = .Always16 },
|
||||
{ opname = .LDS, desc = "", mask = 0b11111111, encoding = 0b11000101,
|
||||
dst = .Register, src = .RegisterMemory,
|
||||
reg_info = .SecondByteMiddle3, word_size = .Always16 },
|
||||
{ opname = .LES, desc = "", mask = 0b11111111, encoding = 0b11000100,
|
||||
dst = .Register, src = .RegisterMemory,
|
||||
reg_info = .SecondByteMiddle3, word_size = .Always16 },
|
||||
{ opname = .LAHF, desc = "", mask = 0b11111111, encoding = 0b10011111,},
|
||||
{ opname = .SAHF, desc = "", mask = 0b11111111, encoding = 0b10011110,},
|
||||
{ opname = .PUSHF, desc = "", mask = 0b11111111, encoding = 0b10011100,},
|
||||
{ opname = .POPF, desc = "", mask = 0b11111111, encoding = 0b10011101,},
|
||||
{ opname = .INC, desc = "", mask = 0b11111000, encoding = 0b01000000,
|
||||
src = .Register, reg_info = .FirstByteLast3, word_size = .Always16 },
|
||||
{ opname = .AAA, desc = "", mask = 0b11111111, encoding = 0b00110111,},
|
||||
{ opname = .DAA, desc = "", mask = 0b11111111, encoding = 0b00100111,},
|
||||
{ opname = .DEC, desc = "", mask = 0b11111000, encoding = 0b01001000,
|
||||
src = .Register, reg_info = .FirstByteLast3, word_size = .Always16 },
|
||||
{ opname = .AAS, desc = "", mask = 0b11111111, encoding = 0b00111111,},
|
||||
{ opname = .DAS, desc = "", mask = 0b11111111, encoding = 0b00101111,},
|
||||
{ opname = .AAM, desc = "", mask = 0b11111111, encoding = 0b11010100,},
|
||||
{ opname = .AAD, desc = "", mask = 0b11111111, encoding = 0b11010101, consume_extra_bytes = 1 },
|
||||
{ opname = .CBW, desc = "", mask = 0b11111111, encoding = 0b10011000,},
|
||||
{ opname = .CWD, desc = "", mask = 0b11111111, encoding = 0b10011001,},
|
||||
{ opname = .TEST, desc = "", mask = 0b11111100, encoding = 0b10000100,
|
||||
dst = .RegisterMemory, src = .Register,
|
||||
word_size = .LastBit, reg_info = .SecondByteMiddle3, has_flip = true },
|
||||
{ opname = .REP, desc = "", mask = 0b11111110, encoding = 0b11110010, src = .Repeat },
|
||||
{ opname = .RET, desc = "", mask = 0b11111111, encoding = 0b11000011,},
|
||||
{ opname = .RET, src = .Immediate, word_size = .Always16,
|
||||
desc = "", mask = 0b11111111, encoding = 0b11000010,},
|
||||
{ opname = .INT, src = .Immediate, desc = "", mask = 0b11111111, encoding = 0b11001101,},
|
||||
{ opname = .INT3, desc = "", mask = 0b11111111, encoding = 0b11001100,},
|
||||
{ opname = .INTO, desc = "", mask = 0b11111111, encoding = 0b11001110,},
|
||||
{ opname = .IRET, desc = "", mask = 0b11111111, encoding = 0b11001111,},
|
||||
{ opname = .CLC, desc = "", mask = 0b11111111, encoding = 0b11111000,},
|
||||
{ opname = .CMC, desc = "", mask = 0b11111111, encoding = 0b11110101,},
|
||||
{ opname = .STC, desc = "", mask = 0b11111111, encoding = 0b11111001,},
|
||||
{ opname = .CLD, desc = "", mask = 0b11111111, encoding = 0b11111100,},
|
||||
{ opname = .STD, desc = "", mask = 0b11111111, encoding = 0b11111101,},
|
||||
{ opname = .CLI, desc = "", mask = 0b11111111, encoding = 0b11111010,},
|
||||
{ opname = .STI, desc = "", mask = 0b11111111, encoding = 0b11111011,},
|
||||
{ opname = .HLT, desc = "", mask = 0b11111111, encoding = 0b11110100,},
|
||||
{ opname = .WAIT, desc = "", mask = 0b11111111, encoding = 0b10011011,},
|
||||
// { opname = .ESC, desc = "", mask = 0b11111111, encoding = 0b11111000, dst = },
|
||||
{ opname = .LOCK, desc = "", mask = 0b11111111, encoding = 0b11110000,},
|
||||
{ opname = .SEGMENT, desc = "", mask = 0b11100111, encoding = 0b00100110,},
|
||||
{ opname = .JE, mask = 0b11111111, encoding = 0b01110100, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JZ, mask = 0b11111111, encoding = 0b01110100, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JL, mask = 0b11111111, encoding = 0b01111100, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JNGE, mask = 0b11111111, encoding = 0b01111100, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JLE, mask = 0b11111111, encoding = 0b01111110, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JNG, mask = 0b11111111, encoding = 0b01111110, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JB, mask = 0b11111111, encoding = 0b01110010, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JNAE, mask = 0b11111111, encoding = 0b01110010, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JBE, mask = 0b11111111, encoding = 0b01110110, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JNA, mask = 0b11111111, encoding = 0b01110110, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JP, mask = 0b11111111, encoding = 0b01111010, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JPE, mask = 0b11111111, encoding = 0b01111010, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JO, mask = 0b11111111, encoding = 0b01110000, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JS, mask = 0b11111111, encoding = 0b01111000, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNE, mask = 0b11111111, encoding = 0b01110101, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JNZ, mask = 0b11111111, encoding = 0b01110101, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNL, mask = 0b11111111, encoding = 0b01111101, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JGE, mask = 0b11111111, encoding = 0b01111101, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNLE, mask = 0b11111111, encoding = 0b01111111, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JG, mask = 0b11111111, encoding = 0b01111111, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNB, mask = 0b11111111, encoding = 0b01110011, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JAE, mask = 0b11111111, encoding = 0b01110011, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNBE, mask = 0b11111111, encoding = 0b01110111, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JA, mask = 0b11111111, encoding = 0b01110111, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNP, mask = 0b11111111, encoding = 0b01111011, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JPO, mask = 0b11111111, encoding = 0b01111011, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNO, mask = 0b11111111, encoding = 0b01110001, src = .Jump, desc = "Jump on not zero", },
|
||||
|
||||
{ opname = .JNS, mask = 0b11111111, encoding = 0b01111001, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .LOOP, mask = 0b11111111, encoding = 0b11100010, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .LOOPZ, mask = 0b11111111, encoding = 0b11100001, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .LOOPNZ, mask = 0b11111111, encoding = 0b11100000, src = .Jump, desc = "Jump on not zero", },
|
||||
{ opname = .JCXZ, mask = 0b11111111, encoding = 0b11100011, src = .Jump, desc = "Jump on not zero", },
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user