Clean up operand code by removing unnecessary variants
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c312b7fd57
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a91c3d9ba9
@ -8,7 +8,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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operand: Operand = None{}
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switch opinfo {
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case .None:
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case .Register:
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case .Register, .SegmentRegister:
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reg: u8
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switch inst.reg_info {
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case .None: panic("Register is required but the encoded location is not provided")
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@ -17,26 +17,13 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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case .SecondByteMiddle3: reg = (data[1] >> 3) & 0b111
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case .SecondByteLast3: reg = data[1] & 0b111
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}
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if word {
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if opinfo == .SegmentRegister {
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operand = (RegisterId){id = SEGMENT_REGISTER_START + (int)(reg), access = .Full}
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} else if word {
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operand = RegisterId { id = (int)(reg), access = .Full }
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} else {
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operand = RegisterId { id = (int)(reg % 4), access = reg < 4 ? .Low : .High }
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}
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case .SegmentRegister:
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reg: u8
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switch inst.reg_info {
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case .None:
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panic("Register is required but the encoded location is not provided")
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case .FirstByteLast3:
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reg = data[0] & 0b111
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case .FirstByteMiddle3:
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reg = (data[0] >> 3) & 0b111
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case .SecondByteMiddle3:
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reg = (data[1] >> 3) & 0b111
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case .SecondByteLast3:
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reg = data[1] & 0b111
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}
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operand = (SegmentRegister)(segment_registers[reg].code)
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case .RegisterMemory:
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mod := data[1] >> 6
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rm := data[1] & 0b111
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@ -44,6 +31,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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op: Operand
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if mod == 0 {
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if rm == 0b110 {
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// op = DirectAddress { value = get_i16(data[2:]) }
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op = (DirectAddress)(get_i16(data[2:]))
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processed^ += 2
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} else {
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@ -69,14 +57,16 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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if inst.has_sign_extension {
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word_signed &&= data[0] & 0b0000_0010 == 0
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}
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operand = (Operand)(word_signed ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx]))
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value: u16 = word_signed ? u16(get_i16(data[data_idx:])) : u16(data[data_idx])
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operand = Immediate { value = value, size = word_signed ? .Signed16 : .Signed8 }
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processed^ += word_signed ? 2 : 1
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case .ImmediateUnsigned:
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operand = (ImmediateU8)(data[processed^])
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operand = Immediate { value = u16(data[processed^]), size = .Unsigned8 }
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processed^ += 1
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case .Accumulator:
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operand = RegisterId { id = 0, access = word ? .Full : .Low }
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case .DirectAddress:
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// operand = DirectAddress { value = get_i16(data[1:]) }
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operand = (DirectAddress)(get_i16(data[1:]))
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processed^ += 2
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case .Jump:
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@ -84,16 +74,16 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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// NOTE: In order to mimic the label offset, you have to take the value you got and add two
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operand = (Jump)((i8)(data[1]) + 2)
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case .VariablePort:
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operand = VariablePort{}
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operand = RegisterId { id = (int)(variable_port.code), access = .Full }
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case .ShiftRotate:
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v_flag := data[0] & 0b10 != 0
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operand = (ShiftRotate)(v_flag)
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operand = v_flag ? RegisterId { id = 1, access = .Low } : Immediate { value = 1 }
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case .Repeat:
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operand = get_repeat_op(data[1])
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processed^ += 1
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case .DirectWithinSegment:
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value := (int)(get_i16(data[1:])) + total_bytes_processed + 3
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operand = (DirectWithinSegment)(value)
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operand = Immediate { value = u16(value), size = .Signed16 }
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processed^ += 2
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case .Intersegment:
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operand = Intersegment {
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@ -133,7 +123,7 @@ decode_data :: proc(inst_list: ^[dynamic]Instruction, data: []u8, bytes_to_read:
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continue
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} else if inst.opname == .SEGMENT {
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reg := (curr_byte & 0b11000) >> 3
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has_segment = segment_registers[reg]
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has_segment = registers[SEGMENT_REGISTER_START+reg]
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idx += 1
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continue
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} else if inst.opname == .AAM {
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@ -152,7 +142,6 @@ decode_data :: proc(inst_list: ^[dynamic]Instruction, data: []u8, bytes_to_read:
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word: bool
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flip: bool
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indirect_intersegment: bool
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op: Operand
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if inst.has_flip {
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@ -11,20 +11,17 @@ execute_instruction :: proc(inst: Instruction) {
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if reg_id,ok := inst.dst.(RegisterId); ok {
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// val := registers[reg_id.id].value.full
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#partial switch val in inst.src {
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case Immediate8:
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if reg_id.access == .Low {
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registers[reg_id.id].value.low = (u8)(val)
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case Immediate:
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if val.size == .Signed16 {
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registers[reg_id.id].value.full = (u16)(val.value)
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} else {
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registers[reg_id.id].value.high = (u8)(val)
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}
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case ImmediateU8:
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value := u8(val.value & 0xFF)
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if reg_id.access == .Low {
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registers[reg_id.id].value.low = (u8)(val)
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registers[reg_id.id].value.low = value
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} else {
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registers[reg_id.id].value.high = (u8)(val)
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registers[reg_id.id].value.high = value
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}
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}
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case Immediate16:
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registers[reg_id.id].value.full = (u16)(val)
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case RegisterId:
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switch val.access {
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case .Low, .High:
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@ -37,23 +34,7 @@ execute_instruction :: proc(inst: Instruction) {
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case .Full:
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registers[reg_id.id].value.full = registers[val.id].value.full
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}
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case SegmentRegister:
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registers[reg_id.id].value.full = segment_registers[val].value.full
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}
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// fmt.printfln("%s:%04x->%04x", registers[reg_id].fullname, val, registers[reg_id].value.full)
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} else if reg_id,ok := inst.dst.(SegmentRegister); ok {
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// val := segment_registers[reg_id].value.full
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#partial switch val in inst.src {
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case Immediate8:
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segment_registers[reg_id].value.low = (u8)(val)
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case ImmediateU8:
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segment_registers[reg_id].value.low = (u8)(val)
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case Immediate16:
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segment_registers[reg_id].value.full = (u16)(val)
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case RegisterId:
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segment_registers[reg_id].value.full = registers[val.id].value.full
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}
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// fmt.printfln("%s:%04x->%04x", segment_registers[reg_id].fullname, val, segment_registers[reg_id].value.full)
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}
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}
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}
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}
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@ -141,8 +141,15 @@ get_operand_string :: proc(operand: Operand, has_segment: Maybe(Register)) -> st
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string_val = ""
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case RegisterId:
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string_val = get_register_name(val)
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case Immediate8, ImmediateU8, Immediate16, DirectWithinSegment:
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string_val = fmt.aprintf("%d", val)
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case Immediate:
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switch val.size {
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case .Signed8:
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string_val = fmt.aprintf("%d", i8(val.value))
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case .Unsigned8:
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string_val = fmt.aprintf("%d", u8(val.value))
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case .Signed16:
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string_val = fmt.aprintf("%d", i16(val.value))
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}
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case MemoryAddr:
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string_val = get_memory_string(val, has_segment)
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case DirectAddress:
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@ -151,14 +158,8 @@ get_operand_string :: proc(operand: Operand, has_segment: Maybe(Register)) -> st
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seg_string = fmt.aprintf("%s:", segreg.fullname)
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}
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string_val = fmt.aprintf("%s[%d]", seg_string, val)
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case SegmentRegister:
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string_val = segment_registers[val].fullname
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case Jump:
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string_val = fmt.aprintf("$%s%d", val >= 0 ? "+" : "", val)
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case VariablePort:
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string_val = variable_port.fullname
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case ShiftRotate:
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string_val = val ? "cl" : "1"
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case Repeat:
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string_val = (string)(val)
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case Intersegment:
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@ -176,10 +177,10 @@ get_unknown_inst_string :: proc(inst: Instruction) -> string {
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get_instruction_string :: proc(inst_info: InstructionInfo, instruction: Instruction) {
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inst := instruction
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src_is_imm := operand_is(Immediate8, inst.src) || operand_is(Immediate16, inst.src)
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src_is_imm := operand_is(Immediate, inst.src)
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dst_is_bracketed := operand_is(MemoryAddr, inst.dst) || operand_is(DirectAddress, inst.dst)
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src_is_bracketed := operand_is(MemoryAddr, inst.src) || operand_is(DirectAddress, inst.src)
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shiftrot := operand_is(ShiftRotate, inst.src)
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shiftrot := inst_info.opname == .TBD6
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size_string := ""
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if ((src_is_imm && dst_is_bracketed) || (dst_is_bracketed && shiftrot)) || (src_is_bracketed && operand_is(None, inst.dst)) {
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size_string = inst.is_word ? "word " : "byte "
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10
sim8086.odin
10
sim8086.odin
@ -12,7 +12,7 @@ RIGHT_ALIGN_AMOUNT := 35
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// We have to change how we coded this out. Likely we have to remove bytename as an option
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// and then have some kind of flag when you're doing a dst or src operand specifying
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// if it's the high or low part, not sure how to go about that
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registers := [8]Register {
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registers := [?]Register {
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{fullname = "ax", code = 0b000},
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{fullname = "cx", code = 0b001},
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{fullname = "dx", code = 0b010},
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@ -21,9 +21,6 @@ registers := [8]Register {
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{fullname = "bp", code = 0b101},
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{fullname = "si", code = 0b110},
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{fullname = "di", code = 0b111},
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}
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segment_registers := [4]Register {
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{fullname = "es", code = 0b000},
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{fullname = "cs", code = 0b001},
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{fullname = "ss", code = 0b010},
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@ -32,6 +29,8 @@ segment_registers := [4]Register {
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variable_port := registers[2]
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SEGMENT_REGISTER_START :: 8
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// TODO: I don't like this here
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total_bytes_processed := 0
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get_i16 :: proc(data: []u8) -> i16 {
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@ -108,9 +107,6 @@ main :: proc() {
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for reg in registers {
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print_reg(reg)
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}
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for reg in segment_registers {
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print_reg(reg)
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}
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}
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if what_to_print == "instructions" || what_to_print == "all" {
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print_instructions_stdout(instructions_list[:])
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@ -13,7 +13,7 @@ fi
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for ASM_BIN in asm_files/*.bin;
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do
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./sim8086 "$ASM_BIN" > output.asm 2> /dev/null
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./sim8086 "$ASM_BIN" instructions > output.asm 2> /dev/null
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nasm output.asm -o output.bin 2> /dev/null
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ASM_FILE=${ASM_BIN%.*}.asm
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if [ ! -e output.bin ]; then
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28
types.odin
28
types.odin
@ -39,39 +39,35 @@ RegisterId :: struct {
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access: RegisterAccess,
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id: int,
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}
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Immediate8 :: distinct i8
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Immediate16 :: distinct i16
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ImmediateU8 :: distinct u8
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ImmediateSize :: enum {
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Signed8,
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Unsigned8,
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Signed16,
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}
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Immediate :: struct {
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value: u16,
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size: ImmediateSize,
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}
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MemoryAddr :: struct {
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addr_id: u8,
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displacement: Displacement,
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}
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DirectAddress :: distinct i16
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SegmentRegister :: distinct i16
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Jump :: distinct i8
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VariablePort :: struct {}
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ShiftRotate :: distinct bool
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Repeat :: string
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Intersegment :: struct {
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ip: i16,
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cs: i16,
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}
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DirectWithinSegment :: distinct u16
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Operand :: union {
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None,
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RegisterId,
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Immediate8,
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ImmediateU8,
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Immediate16,
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Immediate,
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MemoryAddr,
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DirectAddress,
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SegmentRegister,
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Jump,
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VariablePort,
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ShiftRotate,
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Repeat,
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DirectWithinSegment,
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Intersegment,
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}
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@ -122,7 +118,9 @@ Instruction :: struct {
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dst: Operand,
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info: InstructionInfo,
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is_word: bool,
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indirect_intersegment: bool,
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// indirect_intersegment: bool,
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// TODO: This is trickier than I thought, it's more than just the one instruction
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// that uses it
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has_segment: Maybe(Register),
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has_lock: bool,
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bytes_read: int,
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