Add new listings, supply cs register, fix segreg mov instruction

asm_files/list-0043.txt

@@ -17,3 +17,7 @@ Final registers:
       bp: 0x0006 (6)
       si: 0x0007 (7)
       di: 0x0008 (8)
+      es: 0x0000 (0)
+      ss: 0x0000 (0)
+      cs: 0x0000 (0)
+      ds: 0x0000 (0)

asm_files/list-0044.txt

@@ -21,3 +21,7 @@ Final registers:
       bp: 0x0002 (2)
       si: 0x0003 (3)
       di: 0x0004 (4)
+      es: 0x0000 (0)
+      ss: 0x0000 (0)
+      cs: 0x0000 (0)
+      ds: 0x0000 (0)

asm_files/list-0045.asm

@@ -0,0 +1,43 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 45
+; ========================================================================
+
+bits 16
+
+mov ax, 0x2222
+mov bx, 0x4444
+mov cx, 0x6666
+mov dx, 0x8888
+
+mov ss, ax
+mov ds, bx
+mov es, cx
+
+mov al, 0x11
+mov bl, 0x33
+mov cl, 0x55
+mov dl, 0x77
+
+mov al, bl
+mov cl, dh
+
+mov ss, ax
+mov ds, bx
+mov es, cx
+
+mov sp, ss
+mov bp, ds
+mov si, es
+mov di, dx

asm_files/list-0045.txt

@@ -0,0 +1,35 @@
+--- test\listing_0045_challenge_register_movs execution ---
+mov ax, 8738 ; ax:0x0->0x2222 
+mov bx, 17476 ; bx:0x0->0x4444 
+mov cx, 26214 ; cx:0x0->0x6666 
+mov dx, 34952 ; dx:0x0->0x8888 
+mov ss, ax ; ss:0x0->0x2222 
+mov ds, bx ; ds:0x0->0x4444 
+mov es, cx ; es:0x0->0x6666 
+mov al, 17 ; ax:0x2222->0x2211 
+mov bh, 51 ; bx:0x4444->0x3344 
+mov cl, 85 ; cx:0x6666->0x6655 
+mov dh, 119 ; dx:0x8888->0x7788 
+mov ah, bl ; ax:0x2211->0x4411 
+mov cl, dh ; cx:0x6655->0x6677 
+mov ss, ax ; ss:0x2222->0x4411 
+mov ds, bx ; ds:0x4444->0x3344 
+mov es, cx ; es:0x6666->0x6677 
+mov sp, ss ; sp:0x0->0x4411 
+mov bp, ds ; bp:0x0->0x3344 
+mov si, es ; si:0x0->0x6677 
+mov di, dx ; di:0x0->0x7788 
+
+Final registers:
+      ax: 0x4411 (17425)
+      bx: 0x3344 (13124)
+      cx: 0x6677 (26231)
+      dx: 0x7788 (30600)
+      sp: 0x4411 (17425)
+      bp: 0x3344 (13124)
+      si: 0x6677 (26231)
+      di: 0x7788 (30600)
+      es: 0x6677 (26231)
+      ss: 0x4411 (17425)
+      cs: 0x0000 (0)
+      ds: 0x3344 (13124)

instructions.odin

@@ -154,10 +154,12 @@ instructions := [?]InstructionInfo {
       mask = 0b11111110, encoding = 0b10100010,
       dst = .DirectAddress, src = .Accumulator,
       word_size = .LastBit, },
-    { opname = .MOV, desc = "Accumulator to memory",
+    // NOTE: There's another instruction but it seems like it just flips, and while not specified
-      mask = 0b11111111, encoding = 0b10001100,
+    // it seems like it has an undocumented flip bit just like the others
+    { opname = .MOV, desc = "Register/memory to segment register",
+      mask = 0b11111101, encoding = 0b10001100,
       dst = .RegisterMemory, src = .SegmentRegister,
-      reg_info = .SecondByteMiddle3 },
+      reg_info = .SecondByteMiddle3, word_size = .Always16, has_flip = true },
     { opname = .PUSH, desc = "", mask = 0b11111000, encoding = 0b01010000,
       src = .Register, reg_info = .FirstByteLast3,
       word_size = .Always16, },

sim8086.odin

@@ -91,16 +91,21 @@ main :: proc() {
     }
 
     if true {
-        for reg in registers {
+        print_reg :: proc(reg: Register) {
             full := fmt.aprintf("%s (%s): %d ", reg.fullname, reg.bytename, reg.value.full)
-            // hex := fmt.aprintf("%s %*[1]s 0x%x ", full, 25 - len(full), "|", reg.value.full)
             hex := fmt.aprintf("0x%04x ", reg.value.full)
             fmt.printf("%s %*[1]s %s %*[4]s %08b %08b",
-                       full, 20 - len(full), "|", hex, 10 - len(hex), "|", reg.value.high, reg.value.low)
+                       full, 18 - len(full), "|", hex, 10 - len(hex), "|", reg.value.high, reg.value.low)
             fmt.println()
         }
+        for reg in registers {
+            print_reg(reg)
         }
-    if true {
+        for reg in segment_registers {
-        // print_instructions_stdout(instructions_list[:])
+            print_reg(reg)
+        }
+    }
+    if false {
+        print_instructions_stdout(instructions_list[:])
     }
 }

types.odin

@@ -39,7 +39,7 @@ MemoryAddr :: struct {
     displacement: Displacement,
 }
 DirectAddress :: distinct i16
-SegmentRegister :: distinct i8
+SegmentRegister :: distinct i16
 Jump :: distinct i8
 VariablePort :: struct {}
 ShiftRotate :: distinct bool