Generalize with perform_load and perform_store, use bit_set for cpu flags
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831a307975
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df105ea3cf
195
execution.odin
195
execution.odin
@ -23,7 +23,7 @@ get_effective_address_value :: proc(cpu: ^Cpu, id: u8) -> i16 {
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return -1
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}
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get_operand_value :: proc(cpu: ^Cpu, operand: Operand) -> i16 {
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perform_load :: proc(cpu: ^Cpu, operand: Operand, is_word: bool) -> i16 {
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#partial switch opr in operand {
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case Immediate:
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return i16(opr.value)
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@ -36,139 +36,74 @@ get_operand_value :: proc(cpu: ^Cpu, operand: Operand) -> i16 {
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return i16(reg_val.full)
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}
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case DirectAddress:
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value := i16(u16(cpu.memory[opr+1] << 8) | u16(cpu.memory[opr]))
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value: i16
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if is_word {
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value = i16(u16(cpu.memory[opr+1] << 8) | u16(cpu.memory[opr]))
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} else {
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value = i16(cpu.memory[opr])
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}
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return value
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case MemoryAddr:
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value: i16
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idx := get_effective_address_value(cpu, opr.addr_id) + opr.displacement
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value := i16(u16(cpu.memory[idx+1] << 8) | u16(cpu.memory[idx]))
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// fmt.println("Checking", idx)
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// for i in 0..<6 {
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// fmt.printf("%04x ", cpu.memory[int(idx)-3+i])
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// }
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// fmt.println()
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if is_word {
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value = i16(u16(cpu.memory[idx+1] << 8) | u16(cpu.memory[idx]))
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} else {
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value = i16(cpu.memory[idx])
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}
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return value
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}
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return 0
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}
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set_register_value :: proc(cpu: ^Cpu, reg: RegisterId, value: i16) {
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switch reg.access {
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case .Low:
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cpu.registers[reg.name].low = u8(value)
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case .High:
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cpu.registers[reg.name].high = u8(value)
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case .Full:
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cpu.registers[reg.name].full = i16(value)
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check_flags :: proc(cpu: ^Cpu, flags: bit_set[Flag], dst: i16, src: i16, result: i16, is_add: bool) {
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if .ZF in flags do cpu.flags[.ZF] = result == 0
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if .SF in flags do cpu.flags[.SF] = (result >> 15) & 0x1 == 1
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if .CF in flags {
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cpu.flags[.CF] = is_add ? u32(dst) + u32(src) > 0xFFFF : src > dst
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}
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}
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get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
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reg,_ := reflect.enum_from_name(Register, name)
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return &cpu.registers[reg]
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}
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check_zero_flag :: proc(cpu: ^Cpu, value: i16) {
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cpu.flags[.ZF] = value == 0
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}
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check_sign_flag :: proc(cpu: ^Cpu, value: i16) {
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cpu.flags[.SF] = (value >> 15) & 0x1 == 1
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}
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check_carry_flag :: proc(cpu: ^Cpu, dst: i16, src: i16, is_add: bool) {
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cpu.flags[.CF] = is_add ? u32(dst) + u32(src) > 0xFFFF : src > dst
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}
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check_parity_flag :: proc(cpu: ^Cpu, value: i16) {
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val := value
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bit_count := 0
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val &= 0x00FF
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for val != 0 {
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if val & 0x1 == 1 {
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bit_count += 1
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if .AF in flags {
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lhs, rhs := dst & 0xF, src & 0xF
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cpu.flags[.AF] = is_add ? lhs + rhs > 15 : lhs < rhs
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}
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if .PF in flags {
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val := result
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bit_count := 0
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val &= 0x00FF
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for val != 0 {
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if val & 0x1 == 1 {
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bit_count += 1
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}
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val >>= 1
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}
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val >>= 1
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cpu.flags[.PF] = bit_count % 2 == 0
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}
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cpu.flags[.PF] = bit_count % 2 == 0
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}
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check_auxiliary_carry_flag :: proc(cpu: ^Cpu, dst: i16, src: i16, is_add: bool) {
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lhs, rhs := dst & 0xF, src & 0xF
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cpu.flags[.AF] = is_add ? lhs + rhs > 15 : lhs < rhs
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}
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check_flags :: proc(cpu: ^Cpu, value: i16) {
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check_zero_flag(cpu, value)
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check_sign_flag(cpu, value)
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check_parity_flag(cpu, value)
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perform_store :: proc(cpu: ^Cpu, value: i16, operand: Operand, is_word: bool) {
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#partial switch opr in operand {
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case RegisterId:
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switch opr.access {
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case .Low:
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cpu.registers[opr.name].low = u8(value)
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case .High:
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cpu.registers[opr.name].high = u8(value)
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case .Full:
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cpu.registers[opr.name].full = i16(value)
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}
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case DirectAddress:
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cpu.memory[opr] = u8(value)
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if is_word do cpu.memory[opr+1] = u8((u16(value) & 0xFF00) >> 8)
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case MemoryAddr:
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effective_addr_val := get_effective_address_value(cpu, opr.addr_id)
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addr := effective_addr_val + opr.displacement
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cpu.memory[addr] = u8(value)
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if is_word do cpu.memory[addr+1] = u8((u16(value) & 0xFF00) >> 8)
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}
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}
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execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
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if reg,ok := inst.dst.(RegisterId); ok {
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#partial switch inst.opname {
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case .MOV:
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src_val := get_operand_value(cpu, inst.src)
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set_register_value(cpu, reg, src_val)
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case .ADD:
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src_val := get_operand_value(cpu, inst.src)
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dst_val := get_operand_value(cpu, inst.dst)
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val := i16(cpu.registers[reg.name].full) + src_val
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set_register_value(cpu, reg, val)
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check_flags(cpu, val)
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check_auxiliary_carry_flag(cpu, dst_val, src_val, true)
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check_carry_flag(cpu, dst_val, src_val, true)
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case .SUB:
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src_val := get_operand_value(cpu, inst.src)
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dst_val := get_operand_value(cpu, inst.dst)
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val := i16(cpu.registers[reg.name].full) - src_val
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set_register_value(cpu, reg, val)
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check_flags(cpu, val)
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check_auxiliary_carry_flag(cpu, dst_val, src_val, false)
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check_carry_flag(cpu, dst_val, src_val, false)
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case .CMP:
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src_val := get_operand_value(cpu, inst.src)
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dst_val := get_operand_value(cpu, inst.dst)
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val := i16(cpu.registers[reg.name].full) - src_val
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check_flags(cpu, val)
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check_auxiliary_carry_flag(cpu, dst_val, src_val, false)
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check_carry_flag(cpu, dst_val, src_val, false)
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}
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} else if addr,ok := inst.dst.(DirectAddress); ok {
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#partial switch inst.opname {
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case .MOV:
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if imm,ok := inst.src.(Immediate); ok {
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if imm.size == ._16 {
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cpu.memory[addr] = u8(imm.value & 0x00FF)
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cpu.memory[addr+1] = u8((u16(imm.value) & 0xFF00) >> 8)
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} else {
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cpu.memory[addr] = u8(imm.value)
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}
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}
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}
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} else if mem_addr,ok := inst.dst.(MemoryAddr); ok {
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#partial switch inst.opname {
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case .MOV:
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value := get_operand_value(cpu, inst.src)
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effective_addr_val := get_effective_address_value(cpu, mem_addr.addr_id)
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addr := effective_addr_val + mem_addr.displacement
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cpu.memory[addr] = u8(value & 0x00FF)
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cpu.memory[addr+1] = u8((u16(value) & 0xFF00) >> 8)
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// TODO: We need a way to detect if it's a byte or a word
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// if imm,ok := inst.src.(Immediate); ok {
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// // TODO: We need a function that returns the registers to check out
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// effective_addr_val := get_effective_address_value(cpu, mem_addr.addr_id)
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// addr := effective_addr_val + mem_addr.displacement_value
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// if imm.size == .Signed16 {
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// cpu.memory[addr] = u8(imm.value & 0x00FF)
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// cpu.memory[addr+1] = u8((u16(imm.value) & 0xFF00) >> 8)
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// } else {
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// cpu.memory[addr] = u8(imm.value)
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// }
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// }
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}
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} else if jmp_offset,ok := inst.src.(Jump); ok {
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if jmp_offset,ok := inst.src.(Jump); ok {
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jump: bool
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#partial switch inst.opname {
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case .JNZ, .JNE: jump = !cpu.flags[.ZF]
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@ -187,6 +122,30 @@ execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
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cpu.registers[.ip].full += i16(jmp_offset)
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cpu.registers[.ip].full -= i16(inst.bytes_read)
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}
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return
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}
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status_flags := bit_set[Flag]{.OF, .SF, .ZF, .AF, .PF, .CF}
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#partial switch inst.opname {
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case .MOV:
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src_val := perform_load(cpu, inst.src, inst.is_word)
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perform_store(cpu, src_val, inst.dst, inst.is_word)
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case .ADD:
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src_val := perform_load(cpu, inst.src, inst.is_word)
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dst_val := perform_load(cpu, inst.dst, inst.is_word)
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val := dst_val + src_val
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perform_store(cpu, val, inst.dst, inst.is_word)
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check_flags(cpu, status_flags, dst_val, src_val, val, true)
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case .SUB:
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src_val := perform_load(cpu, inst.src, inst.is_word)
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dst_val := perform_load(cpu, inst.dst, inst.is_word)
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val := dst_val - src_val
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perform_store(cpu, val, inst.dst, inst.is_word)
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check_flags(cpu, status_flags, dst_val, src_val, val, false)
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case .CMP:
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src_val := perform_load(cpu, inst.src, inst.is_word)
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dst_val := perform_load(cpu, inst.dst, inst.is_word)
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val := dst_val - src_val
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check_flags(cpu, status_flags, dst_val, src_val, val, false)
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}
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}
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@ -70,7 +70,7 @@ get_operand_string :: proc(operand: Operand, has_segment: Maybe(RegisterId)) ->
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case RegisterId:
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string_val = get_register_name(val)
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case Immediate:
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string_val = fmt.aprintf("%d", i16(val.value))
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string_val = fmt.aprintf("%d", val.value)
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case MemoryAddr:
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string_val = get_memory_string(val, has_segment)
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case DirectAddress:
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@ -7,6 +7,11 @@ import "core:strings"
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import "core:strconv"
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import "core:reflect"
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get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
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reg,_ := reflect.enum_from_name(Register, name)
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return &cpu.registers[reg]
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}
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parse_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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cpu: Cpu
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@ -68,6 +68,7 @@ Immediate :: struct {
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MemoryAddr :: struct {
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addr_id: u8,
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displacement: i16,
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disp_size: ImmediateSize,
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}
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DirectAddress :: distinct i16
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Jump :: distinct i8
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@ -119,6 +120,7 @@ InstructionInfo :: struct {
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desc: string,
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src: OperandInfo,
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dst: OperandInfo,
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flags: bit_set[Flag],
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word_size: WordSize,
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reg_info: RegisterEncodingBits,
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has_flip: bool,
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