package sim_8086 import "core:os" import "core:path" import "core:fmt" import "core:math" import "core:strings" CPU := Cpu { registers = [12]Register { {fullname = "ax", code = 0b000}, {fullname = "cx", code = 0b001}, {fullname = "dx", code = 0b010}, {fullname = "bx", code = 0b011}, {fullname = "sp", code = 0b100}, {fullname = "bp", code = 0b101}, {fullname = "si", code = 0b110}, {fullname = "di", code = 0b111}, {fullname = "es", code = 0b000}, {fullname = "cs", code = 0b001}, {fullname = "ss", code = 0b010}, {fullname = "ds", code = 0b011}, }, memory = make([dynamic]u8, 65536), } variable_port := CPU.registers[2] main :: proc() { f,err := os.open(os.args[1]) if err != os.ERROR_NONE { fmt.eprintln("ERROR:", err) os.exit(1) } defer os.close(f) what_to_print := len(os.args) >= 3 ? os.args[2] : "" data := make([]u8, 1024) bytes_read, err2 := os.read(f, data) if err2 != nil { // ... os.exit(1) } // asdf :u16 = 0b00000110_11011101 // asdf2 :i16 = (i16)(asdf) // fmt.printfln("%d", asdf2) print_at_end := false line_count := 0 instruction_list := make([dynamic]string, 0, 512) instructions_list := make([dynamic]Instruction, 0, 512) decode_data(&instructions_list, data[:], bytes_read) for inst in instructions_list { execute_instruction(inst) } if what_to_print == "registers" || what_to_print == "all" { print_reg :: proc(reg: Register) { full := fmt.aprintf("%s: %d ", reg.fullname, reg.value.full) hex := fmt.aprintf("0x%04x ", reg.value.full) fmt.printf("%s %*[1]s %s %*[4]s %08b %08b", full, 18 - len(full), "|", hex, 10 - len(hex), "|", reg.value.high, reg.value.low) fmt.println() } for reg in CPU.registers { print_reg(reg) } // fmt.println("Checking Against Expected State") // fmt.println(os.args[1]) // path := path.base_no_ext(os.args[1]) // fmt.println(path) // extract_expected_cpu_state(path) } if what_to_print == "instructions" || what_to_print == "all" { print_instructions_stdout(instructions_list[:]) } }