package sim_8086 import "core:os" import "core:fmt" import "core:math" import "core:strings" execute_instruction :: proc(inst: Instruction) { #partial switch inst.opname { case .MOV: if reg_id,ok := inst.dst.(RegisterId); ok { // val := registers[reg_id.id].value.full #partial switch val in inst.src { case Immediate8: if reg_id.access == .Low { registers[reg_id.id].value.low = (u8)(val) } else { registers[reg_id.id].value.high = (u8)(val) } case ImmediateU8: if reg_id.access == .Low { registers[reg_id.id].value.low = (u8)(val) } else { registers[reg_id.id].value.high = (u8)(val) } case Immediate16: registers[reg_id.id].value.full = (u16)(val) case RegisterId: switch val.access { case .Low, .High: value := val.access == .Low ? registers[val.id].value.low : registers[val.id].value.high if reg_id.access == .Low { registers[reg_id.id].value.low = value } else { registers[reg_id.id].value.high = value } case .Full: registers[reg_id.id].value.full = registers[val.id].value.full } case SegmentRegister: registers[reg_id.id].value.full = segment_registers[val].value.full } // fmt.printfln("%s:%04x->%04x", registers[reg_id].fullname, val, registers[reg_id].value.full) } else if reg_id,ok := inst.dst.(SegmentRegister); ok { // val := segment_registers[reg_id].value.full #partial switch val in inst.src { case Immediate8: segment_registers[reg_id].value.low = (u8)(val) case ImmediateU8: segment_registers[reg_id].value.low = (u8)(val) case Immediate16: segment_registers[reg_id].value.full = (u16)(val) case RegisterId: segment_registers[reg_id].value.full = registers[val.id].value.full } // fmt.printfln("%s:%04x->%04x", segment_registers[reg_id].fullname, val, segment_registers[reg_id].value.full) } } }