612 lines
17 KiB
Odin
612 lines
17 KiB
Odin
package decoder_8086
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import "core:os"
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import "core:fmt"
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import "core:math"
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import "core:strings"
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Register :: struct {
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fullname: string,
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bytename: string,
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value: struct #raw_union {
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using _: struct {
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low, high: byte,
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},
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full: u16,
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},
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code: u8,
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}
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WordSize :: enum {
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None,
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LastBit,
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FourthBit,
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Always8,
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Always16,
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}
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None :: struct {}
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Disp8 :: i8
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Disp16 :: i16
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Displacement :: union {
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None,
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Disp8,
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Disp16
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}
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RegisterId :: distinct u8
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Immediate8 :: distinct i8
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Immediate16 :: distinct i16
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ImmediateU8 :: distinct u8
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MemoryAddr :: struct {
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addr_id: u8,
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displacement: Displacement,
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}
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DirectAddress :: distinct i16
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SegmentRegister :: distinct i8
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Jump :: distinct i8
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VariablePort :: struct {}
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ShiftRotate :: distinct bool
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Repeat :: string
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Intersegment :: struct {
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ip: i16,
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cs: i16,
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}
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DirectWithinSegment :: distinct u16
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Operand :: union {
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None,
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RegisterId,
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Immediate8,
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ImmediateU8,
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Immediate16,
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MemoryAddr,
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DirectAddress,
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SegmentRegister,
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Jump,
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VariablePort,
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ShiftRotate,
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Repeat,
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DirectWithinSegment,
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Intersegment,
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}
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OperandInfo :: enum {
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None,
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Register,
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SegmentRegister,
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RegisterMemory,
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Immediate,
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ImmediateUnsigned,
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Accumulator,
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DirectAddress,
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Jump,
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VariablePort,
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ShiftRotate,
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Repeat,
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DirectWithinSegment,
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Intersegment,
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}
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RegisterEncodingBits :: enum {
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None,
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FirstByteLast3,
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SecondByteMiddle3,
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SecondByteLast3,
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FirstByteMiddle3,
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}
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InstructionInfo :: struct {
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mask: u8,
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encoding: u8,
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opname: OpName,
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desc: string,
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src: OperandInfo,
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dst: OperandInfo,
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word_size: WordSize,
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reg_info: RegisterEncodingBits,
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has_flip: bool,
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has_sign_extension: bool,
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check_second_encoding: bool,
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consume_extra_bytes: int,
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shift_rotate_flag: bool,
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}
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RIGHT_ALIGN_AMOUNT := 35
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registers := [8]Register {
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{fullname = "ax", bytename = "al", code = 0b000},
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{fullname = "cx", bytename = "cl", code = 0b001},
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{fullname = "dx", bytename = "dl", code = 0b010},
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{fullname = "bx", bytename = "bl", code = 0b011},
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{fullname = "sp", bytename = "ah", code = 0b100},
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{fullname = "bp", bytename = "ch", code = 0b101},
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{fullname = "si", bytename = "dh", code = 0b110},
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{fullname = "di", bytename = "bh", code = 0b111},
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}
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segment_registers := [4]Register {
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{fullname = "es", code = 0b000},
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{fullname = "cs", code = 0b001},
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{fullname = "ss", code = 0b010},
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{fullname = "ds", code = 0b011},
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}
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variable_port := registers[2]
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total_bytes_processed := 0
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instruction_builder := strings.builder_make()
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get_i16 :: proc(data: []u8) -> i16 {
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return (i16)(data[1]) << 8 | (i16)(data[0])
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}
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operand_is :: proc($T: typeid, opr: Operand) -> bool {
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_, ok := opr.(T)
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return ok
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}
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calculate_effective_address :: proc(r_m: u8) -> string {
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val: string
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switch r_m {
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case 0b000:
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val = "bx + si"
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case 0b001:
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val = "bx + di"
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case 0b010:
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val = "bp + si"
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case 0b011:
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val = "bp + di"
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case 0b100:
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val = "si"
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case 0b101:
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val = "di"
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case 0b110:
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val = "bp"
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case 0b111:
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val = "bx"
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}
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return val
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}
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get_memory_string :: proc(memoryAddr: MemoryAddr, has_segment: Maybe(Register)) -> string {
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disp: string
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switch value in memoryAddr.displacement {
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case None:
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disp = ""
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case Disp8:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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case Disp16:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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}
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seg_string: string
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if segreg, ok := has_segment.?; ok {
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seg_string = fmt.aprintf("%s:", segreg.fullname)
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}
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text := fmt.aprintf("%s[%s%s]", seg_string, calculate_effective_address(memoryAddr.addr_id), disp)
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return text
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}
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parse_displacement :: proc(data: []u8) -> (displacement: Displacement, disp_amount: int) {
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mod := (data[0] & 0b11000000) >> 6
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disp: Displacement = None{}
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amount: int
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switch mod {
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case 1:
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disp = (i8)(data[1])
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amount = 1
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case 2:
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disp = get_i16(data[1:])
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amount = 2
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}
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return disp, amount
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}
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get_displacement_string :: proc(displacement: Displacement) -> string {
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disp := ""
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#partial switch value in displacement {
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case i8:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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case i16:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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}
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return disp
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}
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get_repeat_op :: proc(data: u8) -> Repeat {
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bits := (data & 0b1110) >> 1
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w := (data & 0b1) == 1 ? "w" : "b"
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rep: string
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switch bits {
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case 0b010: rep = "movs"
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case 0b011: rep = "cmps"
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case 0b101: rep = "stos"
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case 0b110: rep = "lods"
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case 0b111: rep = "scas"
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}
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return Repeat(fmt.aprintf("%s%s", rep, w))
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}
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try_find_instruction :: proc(b: u8) -> (InstructionInfo, bool) {
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for inst in instructions {
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if inst.encoding == (b & inst.mask) {
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return inst, true
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}
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}
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return InstructionInfo{}, false
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}
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get_opname :: proc(opname: OpName, data: []u8) -> (string, bool) {
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name: string
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interseg: bool
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if opname == .TBD2 {
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switch data[1] & 0b00111000 >> 3 {
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case 0b000: name = "inc"
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case 0b001: name = "dec"
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case 0b010: name = "call"
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case 0b011: name = "call"; interseg = true
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case 0b100: name = "jmp"
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case 0b101: name = "jmp"; interseg = true
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case 0b110: name = "push"
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}
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} else if opname == .TBD5 {
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switch data[1] & 0b00111000 >> 3 {
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case 0b000: name = "test"
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case 0b001: name = "dec"
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case 0b010: name = "not"
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case 0b011: name = "neg"
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case 0b100: name = "mul"
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case 0b101: name = "imul"
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case 0b110: name = "div"
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case 0b111: name = "idiv"
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}
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} else if opname == .TBD6 {
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switch data[1] & 0b00111000 >> 3 {
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case 0b000: name = "rol"
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case 0b001: name = "ror"
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case 0b010: name = "rcl"
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case 0b011: name = "rcr"
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case 0b100: name = "shl"
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case 0b101: name = "shr"
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case 0b111: name = "sar"
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}
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} else {
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bits: u8
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if opname == .TBD1 || opname == .TBD3 {
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bits = data[0] & 0b00111000 >> 3
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} else {
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bits = data[1] & 0b00111000 >> 3
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}
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switch bits {
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case 0b000: name = "add"
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case 0b001: name = "or"
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case 0b010: name = "adc"
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case 0b011: name = "sbb"
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case 0b100: name = "and"
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case 0b101: name = "sub"
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case 0b110: name = "xor"
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case 0b111: name = "cmp"
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}
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}
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return name, interseg
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}
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parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, processed: ^int, word: bool, has_segreg: Maybe(Register)) -> Operand {
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operand: Operand = None{}
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switch opinfo {
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case .None:
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case .Register:
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// rm: u8 = data[1] & 0b111
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// dst_opr = (RegisterId)(registers[rm].code)
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reg: u8
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// Read the RegisterEncodingBits
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switch inst.reg_info {
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case .None:
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// panic("Register is required but the encoded location is not provided")
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case .FirstByteLast3:
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reg = data[0] & 0b111
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case .FirstByteMiddle3:
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reg = (data[0] >> 3) & 0b111
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case .SecondByteMiddle3:
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reg = (data[1] >> 3) & 0b111
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case .SecondByteLast3:
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reg = data[1] & 0b111
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}
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operand = (RegisterId)(registers[reg].code)
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case .SegmentRegister:
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reg: u8
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switch inst.reg_info {
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case .None:
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// panic("Register is required but the encoded location is not provided")
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case .FirstByteLast3:
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reg = data[0] & 0b111
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case .FirstByteMiddle3:
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reg = (data[0] >> 3) & 0b111
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case .SecondByteMiddle3:
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reg = (data[1] >> 3) & 0b111
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case .SecondByteLast3:
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reg = data[1] & 0b111
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}
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operand = (SegmentRegister)(segment_registers[reg].code)
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case .RegisterMemory:
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mod := data[1] >> 6
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rm := data[1] & 0b111
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processed^ += 1
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op: Operand
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if mod == 0 {
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if rm == 0b110 {
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op = (DirectAddress)(get_i16(data[2:]))
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processed^ += 2
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} else {
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op = MemoryAddr{ addr_id = rm , displacement = None{} }
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}
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} else if mod == 1 {
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op = MemoryAddr{ addr_id = rm , displacement = (i8)(data[2]) }
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processed^ += 1
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} else if mod == 2 {
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op = MemoryAddr{ addr_id = rm , displacement = get_i16(data[2:]) }
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processed^ += 2
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} else if mod == 3 {
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op = (RegisterId)(registers[rm].code)
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}
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operand = op
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case .Immediate:
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data_idx := processed^
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word_signed := word
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if inst.has_sign_extension {
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word_signed &&= data[0] & 0b0000_0010 == 0
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}
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operand = (Operand)(word_signed ? (Immediate16)(get_i16(data[data_idx:])) : (Immediate8)(data[data_idx]))
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processed^ += word_signed ? 2 : 1
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case .ImmediateUnsigned:
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operand = (ImmediateU8)(data[processed^])
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processed^ += 1
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case .Accumulator:
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operand = (RegisterId)(registers[0].code)
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case .DirectAddress:
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operand = (DirectAddress)(get_i16(data[1:]))
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processed^ += 2
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case .Jump:
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processed^ += 1
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// NOTE: In order to mimic the label offset, you have to take the value you got and add two
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operand = (Jump)((i8)(data[1]) + 2)
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case .VariablePort:
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operand = VariablePort{}
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case .ShiftRotate:
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v_flag := data[0] & 0b10 != 0
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operand = (ShiftRotate)(v_flag)
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case .Repeat:
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operand = get_repeat_op(data[1])
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processed^ += 1
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case .DirectWithinSegment:
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value := (int)(get_i16(data[1:])) + total_bytes_processed + 3
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operand = (DirectWithinSegment)(value)
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processed^ += 2
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case .Intersegment:
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operand = Intersegment {
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ip = get_i16(data[1:]),
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cs = get_i16(data[3:]),
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}
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processed^ += 4
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}
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return operand
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}
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get_operand_string :: proc(operand: Operand, is_word: bool, has_segment: Maybe(Register)) -> string {
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string_val: string
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switch val in operand {
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case None:
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string_val = ""
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case RegisterId:
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string_val = is_word ? registers[val].fullname : registers[val].bytename
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case Immediate8, ImmediateU8, Immediate16, DirectWithinSegment:
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string_val = fmt.aprintf("%d", val)
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case MemoryAddr:
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string_val = get_memory_string(val, has_segment)
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case DirectAddress:
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seg_string: string
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if segreg, ok := has_segment.?; ok {
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seg_string = fmt.aprintf("%s:", segreg.fullname)
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}
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string_val = fmt.aprintf("%s[%d]", seg_string, val)
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case SegmentRegister:
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string_val = segment_registers[val].fullname
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case Jump:
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string_val = fmt.aprintf("$%s%d", val >= 0 ? "+" : "", val)
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case VariablePort:
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string_val = variable_port.fullname
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case ShiftRotate:
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string_val = val ? registers[1].bytename : "1"
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case Repeat:
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string_val = (string)(val)
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case Intersegment:
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string_val = fmt.aprintf("%d:%d", val.cs, val.ip)
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}
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return string_val
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}
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main :: proc() {
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f,err := os.open(os.args[1])
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if err != os.ERROR_NONE {
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fmt.eprintln("ERROR:", err)
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os.exit(1)
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}
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defer os.close(f)
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data := make([]u8, 1024)
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bytes_read, err2 := os.read(f, data)
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if err2 != nil {
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// ...
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os.exit(1)
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}
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if false {
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os.exit(0)
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}
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// asdf :u16 = 0b00000110_11011101
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// asdf2 :i16 = (i16)(asdf)
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// fmt.printfln("%d", asdf2)
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print_at_end := false
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idx := 0
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line_count := 0
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has_lock: bool
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has_segment: Maybe(Register)
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last_opname: [3]byte
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repeating_op_count := 0
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instruction_list := make([dynamic]string, 512)
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fmt.println("bits 16\n")
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for idx < bytes_read {
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processed := 1
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curr_byte := data[idx]
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inst, ok := try_find_instruction(curr_byte)
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if !ok {
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txt := "unknown instruction"
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if print_at_end {
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line := fmt.aprintf("%s %*[1]s %8b", txt, RIGHT_ALIGN_AMOUNT - len(txt), ";;", curr_byte)
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instruction_list[line_count] = line
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line_count += 1
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} else {
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fmt.printfln("%s %*[1]s %8b", txt, RIGHT_ALIGN_AMOUNT - len(txt), ";;", curr_byte)
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}
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idx += 1
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continue
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}
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// Here we check if the instruction affects the next instruction
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if inst.opname == .LOCK {
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has_lock = true
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idx += 1
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continue
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} else if inst.opname == .SEGMENT {
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reg := (curr_byte & 0b11000) >> 3
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has_segment = segment_registers[reg]
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idx += 1
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continue
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} else if inst.opname == .AAM {
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processed += 1
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}
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src_opr: Operand
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dst_opr: Operand
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word: bool
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flip: bool
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indirect_intersegment: bool
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op: Operand
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if inst.has_flip {
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flip = curr_byte & 2 != 0
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}
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#partial switch inst.word_size {
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case .LastBit: word = curr_byte & 1 == 1
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case .FourthBit: word = curr_byte & 0b0000_1000 != 0
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case .Always16: word = true
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}
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opname: string
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if inst.check_second_encoding {
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opname,indirect_intersegment = get_opname(inst.opname, data[idx:])
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// NOTE: This is a special case because it matches the bit pattern of .TBD5,
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// but the instruction itself is different
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if opname == "test" && (curr_byte & 0xFF) == 0b11110110 {
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inst = test_inst
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}
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} else {
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opname = strings.to_lower(fmt.aprintf("%s", inst.opname))
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}
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dst_opr = parse_operand(inst, inst.dst, data[idx:], &processed, word, has_segment)
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src_opr = parse_operand(inst, inst.src, data[idx:], &processed, word, has_segment)
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src_is_imm := operand_is(Immediate8, src_opr) || operand_is(Immediate16, src_opr)
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dst_is_bracketed := operand_is(MemoryAddr, dst_opr) || operand_is(DirectAddress, dst_opr)
|
|
src_is_bracketed := operand_is(MemoryAddr, src_opr) || operand_is(DirectAddress, src_opr)
|
|
shiftrot := inst.src == .ShiftRotate
|
|
size_string := ""
|
|
if ((src_is_imm && dst_is_bracketed) || (dst_is_bracketed && shiftrot)) || (src_is_bracketed && operand_is(None, dst_opr)) {
|
|
size_string = word ? "word " : "byte "
|
|
}
|
|
|
|
if flip {
|
|
src_opr, dst_opr = dst_opr, src_opr
|
|
}
|
|
|
|
dst_str := get_operand_string(dst_opr, word, has_segment)
|
|
src_str := get_operand_string(src_opr, word, has_segment)
|
|
full_inst: string
|
|
if dst_str == "" {
|
|
interseg_string: string
|
|
if indirect_intersegment {
|
|
interseg_string = " far"
|
|
}
|
|
full_inst = fmt.aprintf("%s%s %s%s", opname, interseg_string, size_string, src_str)
|
|
} else {
|
|
// NOTE: I don't know why this is the case, but only the move has the word/byte
|
|
// keyword next to the immediate, but other instructions have it on the memory address
|
|
if opname == "mov" {
|
|
full_inst = fmt.aprintf("%s %s, %s%s", opname, dst_str, size_string, src_str)
|
|
} else {
|
|
full_inst = fmt.aprintf("%s %s%s, %s", opname, size_string, dst_str, src_str)
|
|
}
|
|
}
|
|
|
|
processed += inst.consume_extra_bytes
|
|
|
|
lock_string: string
|
|
if has_lock {
|
|
lock_string = "lock "
|
|
}
|
|
fmt.sbprintf(&instruction_builder, "%s%s %*[2]s", lock_string, full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;")
|
|
if has_lock {
|
|
fmt.sbprintf(&instruction_builder, " lock")
|
|
}
|
|
if _,ok := has_segment.?; ok {
|
|
fmt.sbprintf(&instruction_builder, " segment")
|
|
}
|
|
for i in 0..<processed {
|
|
fmt.sbprintf(&instruction_builder, " %08b", data[idx + i])
|
|
}
|
|
|
|
op2 := strings.to_string(instruction_builder)
|
|
if op2[0:3] != string(last_opname[:]) {
|
|
if repeating_op_count > 0 {
|
|
fmt.println()
|
|
}
|
|
repeating_op_count = 0
|
|
} else {
|
|
repeating_op_count += 1
|
|
}
|
|
copy(last_opname[:], op2[0:3])
|
|
fmt.println(op2)
|
|
|
|
idx += processed
|
|
strings.builder_reset(&instruction_builder)
|
|
has_lock = false
|
|
has_segment = nil
|
|
total_bytes_processed = idx
|
|
}
|
|
if print_at_end {
|
|
for i in 0..<line_count {
|
|
opname := instruction_list[i]
|
|
if !strings.has_prefix(opname, string(last_opname[:])) {
|
|
fmt.println()
|
|
}
|
|
copy(last_opname[:], opname[0:3])
|
|
fmt.println(instruction_list[i])
|
|
}
|
|
}
|
|
}
|