135 lines
4.2 KiB
Odin
135 lines
4.2 KiB
Odin
package sim_8086
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import "core:os"
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import "core:fmt"
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import "core:math"
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import "core:strings"
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import "core:reflect"
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get_ip :: proc(cpu: ^Cpu) -> int { return int(cpu.registers[.ip].full) }
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get_operand_value :: proc(cpu: ^Cpu, operand: Operand) -> i16 {
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#partial switch opr in operand {
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case Immediate:
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// fmt.printfln("0x%4x %d", i16(opr.value), opr.value)
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return i16(opr.value)
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case RegisterId:
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reg_val := cpu.registers[opr.name]
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switch opr.access {
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case .Low, .High:
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return i16(opr.access == .Low ? reg_val.low : reg_val.high)
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case .Full:
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return i16(reg_val.full)
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}
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}
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return 0
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}
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set_register_value :: proc(cpu: ^Cpu, reg: RegisterId, value: i16) {
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switch reg.access {
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case .Low:
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cpu.registers[reg.name].low = u8(value)
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case .High:
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cpu.registers[reg.name].high = u8(value)
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case .Full:
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cpu.registers[reg.name].full = i16(value)
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}
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}
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get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
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reg,_ := reflect.enum_from_name(Register, name)
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return &cpu.registers[reg]
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}
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check_zero_flag :: proc(cpu: ^Cpu, value: i16) {
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cpu.flags[.ZF] = value == 0
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}
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check_sign_flag :: proc(cpu: ^Cpu, value: i16) {
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cpu.flags[.SF] = (value >> 15) & 0x1 == 1
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}
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check_carry_flag :: proc(cpu: ^Cpu, dst: i16, src: i16, is_add: bool) {
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cpu.flags[.CF] = is_add ? u32(dst) + u32(src) > 0xFFFF : src > dst
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}
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check_parity_flag :: proc(cpu: ^Cpu, value: i16) {
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val := value
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bit_count := 0
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val &= 0x00FF
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for val != 0 {
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if val & 0x1 == 1 {
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bit_count += 1
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}
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val >>= 1
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}
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cpu.flags[.PF] = bit_count % 2 == 0
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}
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check_auxiliary_carry_flag :: proc(cpu: ^Cpu, dst: i16, src: i16, is_add: bool) {
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lhs, rhs := dst & 0xF, src & 0xF
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cpu.flags[.AF] = is_add ? lhs + rhs > 15 : lhs < rhs
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}
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check_flags :: proc(cpu: ^Cpu, value: i16) {
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check_zero_flag(cpu, value)
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check_sign_flag(cpu, value)
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check_parity_flag(cpu, value)
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}
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execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
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if reg,ok := inst.dst.(RegisterId); ok {
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#partial switch inst.opname {
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case .MOV:
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src_val := get_operand_value(cpu, inst.src)
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set_register_value(cpu, reg, src_val)
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case .ADD:
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src_val := get_operand_value(cpu, inst.src)
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dst_val := get_operand_value(cpu, inst.dst)
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val := i16(cpu.registers[reg.name].full) + src_val
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set_register_value(cpu, reg, val)
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check_flags(cpu, val)
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check_auxiliary_carry_flag(cpu, dst_val, src_val, true)
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check_carry_flag(cpu, dst_val, src_val, true)
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case .SUB:
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src_val := get_operand_value(cpu, inst.src)
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dst_val := get_operand_value(cpu, inst.dst)
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val := i16(cpu.registers[reg.name].full) - src_val
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set_register_value(cpu, reg, val)
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check_flags(cpu, val)
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check_auxiliary_carry_flag(cpu, dst_val, src_val, false)
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check_carry_flag(cpu, dst_val, src_val, false)
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case .CMP:
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src_val := get_operand_value(cpu, inst.src)
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dst_val := get_operand_value(cpu, inst.dst)
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val := i16(cpu.registers[reg.name].full) - src_val
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check_flags(cpu, val)
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check_auxiliary_carry_flag(cpu, dst_val, src_val, false)
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check_carry_flag(cpu, dst_val, src_val, false)
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}
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} else if jmp_offset,ok := inst.src.(Jump); ok {
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#partial switch inst.opname {
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case .JNZ, .JNE:
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if !cpu.flags[.ZF] {
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cpu.registers[.ip].full += i16(jmp_offset)
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if jmp_offset < 0 {
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cpu.registers[.ip].full -= i16(inst.bytes_read)
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}
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}
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}
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}
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}
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execute_instructions :: proc(cpu: ^Cpu, instructions: DecodedInstructions) {
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halt := false
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fmt.println(instructions.total_bytes_decoded)
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for !halt && get_ip(cpu) < instructions.total_bytes_decoded {
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inst,ok := instructions.inst_map[get_ip(cpu)]
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if !ok {
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// Something went wrong with a jump, most likely
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}
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cpu.registers[.ip].full += i16(inst.bytes_read)
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execute_instruction(cpu, inst)
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}
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}
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