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Fix some of the ported code

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This commit is contained in:
Joseph Ferano 2025-04-17 23:28:08 +08:00
parent a1386a289f
commit 132cc7fb9d
1 changed files with 22 additions and 25 deletions
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45
src/sim6502.rs
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@ -21,7 +21,7 @@ pub enum Addressing {
Relative, Relative,
} }
#[derive(Debug, PartialEq)] #[derive(Debug, Clone, Copy, PartialEq)]
pub enum InstructionName { pub enum InstructionName {
ADC, AHX, ALR, AND, ANC, ARR, ASL, AXS, BCC, BCS, BEQ, BIT, BMI, BNE, BPL, BRK, ADC, AHX, ALR, AND, ANC, ARR, ASL, AXS, BCC, BCS, BEQ, BIT, BMI, BNE, BPL, BRK,
BVC, BVS, CLC, CLD, CLI, CLV, CMP, CPX, CPY, DCP, DEC, DEX, DEY, EOR, ISC, INC, BVC, BVS, CLC, CLD, CLI, CLV, CMP, CPX, CPY, DCP, DEC, DEX, DEY, EOR, ISC, INC,
@ -30,7 +30,7 @@ pub enum InstructionName {
STA, STX, STY, TAS, TAX, TAY, TSX, TXA, TXS, TYA, XAA, STA, STX, STY, TAS, TAX, TAY, TSX, TXA, TXS, TYA, XAA,
} }
#[derive(Debug)] #[derive(Debug, Clone, Copy)]
pub enum AddressingShort { pub enum AddressingShort {
Imp, Acc, Imm, ZPg, ZPX, Imp, Acc, Imm, ZPg, ZPX,
ZPY, Abs, AbX, AbY, InX, ZPY, Abs, AbX, AbY, InX,
@ -43,7 +43,7 @@ pub struct InstructionDefinition {
addressing: AddressingShort, addressing: AddressingShort,
} }
#[derive(Copy, Clone)] #[derive(Debug, Copy, Clone)]
pub enum Register { pub enum Register {
A, A,
X, X,
@ -97,13 +97,13 @@ pub struct Cpu {
} }
#[derive(Debug)] #[derive(Debug)]
pub struct Instruction { pub struct Instruction<'a> {
opcode: u8, opcode: u8,
name: InstructionName, name: InstructionName,
src_opr: Operand, src_opr: Operand,
dst_opr: Operand, dst_opr: Operand,
bytes_read: i32, bytes_read: i32,
raw_data: Vec<u8>, raw_data: &'a [u8],
} }
impl Cpu { impl Cpu {
@ -156,21 +156,17 @@ impl Cpu {
self.status_flags[Carry] = bit > 0x0; self.status_flags[Carry] = bit > 0x0;
} }
pub fn branch(mut self, offset: i8) { pub fn branch_on_flag(&mut self, inst: &Instruction, flag: Flag, not: bool) {
let offset = self.load(&inst.src_opr) as i8;
if not ^ !self.status_flags[flag] {
self.program_counter += 2 + offset as i16; self.program_counter += 2 + offset as i16;
} }
} }
}
macro_rules! instruction_defs { macro_rules! instruction_defs {
($({$name:ident, $addr:ident}),* $(,)?) => { ($({$name:ident, $addr:ident}),* $(,)?) => {
[ [$(InstructionDefinition {name: $name, addressing: $addr},)*]
$(
InstructionDefinition {
name: $name,
addressing: $addr
},
)*
]
}; };
} }
@ -245,7 +241,8 @@ fn execute(cpu: &mut Cpu, inst: &Instruction) {
cpu.registers[reg] = result as u8 - carry_val; cpu.registers[reg] = result as u8 - carry_val;
} }
cpu.status_flags[Carry] = result < 0; // TODO: This is wrong because it's a u16, it can't be below 0
// cpu.status_flags[Carry] = if result < 0 { true } else { false };
let reg_a = cpu.registers[A]; let reg_a = cpu.registers[A];
let res = result as u8; let res = result as u8;
@ -273,18 +270,18 @@ fn execute(cpu: &mut Cpu, inst: &Instruction) {
cpu.check_z_n_flags(cpu.registers[A]); cpu.check_z_n_flags(cpu.registers[A]);
}, },
EOR => { EOR => {
cpu.registers[A] != cpu.load(&inst.src_opr); cpu.registers[A] ^= cpu.load(&inst.src_opr);
cpu.check_z_n_flags(cpu.registers[A]); cpu.check_z_n_flags(cpu.registers[A]);
}, },
// Branching // Branching
BCC => if !cpu.status_flags[Carry] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BCC => cpu.branch_on_flag(&inst, Carry, true),
BCS => if cpu.status_flags[Carry] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BCS => cpu.branch_on_flag(&inst, Carry, false),
BNE => if !cpu.status_flags[Zero] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BNE => cpu.branch_on_flag(&inst, Zero, true),
BEQ => if cpu.status_flags[Zero] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BEQ => cpu.branch_on_flag(&inst, Zero, false),
BPL => if !cpu.status_flags[Negative] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BPL => cpu.branch_on_flag(&inst, Negative, true),
BMI => if cpu.status_flags[Negative] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BMI => cpu.branch_on_flag(&inst, Negative, false),
BVC => if !cpu.status_flags[Overflow] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BVC => cpu.branch_on_flag(&inst, Overflow, true),
BVS => if cpu.status_flags[Overflow] { cpu.branch(cpu.load(&inst.src_opr) as i8) }, BVS => cpu.branch_on_flag(&inst, Overflow, false),
// Jump // Jump
JMP => cpu.program_counter = cpu.load_u16(&inst.src_opr) as i16, JMP => cpu.program_counter = cpu.load_u16(&inst.src_opr) as i16,
JSR => { JSR => {