JosephFerano
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  • Joined on 2023-04-20
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JosephFerano created repository JosephFerano/pmme 2025-06-02 14:39:38 +07:00
JosephFerano pushed to master at JosephFerano/rusted-nes 2025-04-17 22:29:05 +07:00
2068cf08e1 Construct operands src/dst from instruction definition, wip
132cc7fb9d Fix some of the ported code
a1386a289f Get rom path from cli args
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JosephFerano created branch master in JosephFerano/rusted-nes 2025-04-16 23:47:21 +07:00
JosephFerano pushed to master at JosephFerano/rusted-nes 2025-04-16 23:47:21 +07:00
102c08569a First commit, still porting Odin code
JosephFerano created repository JosephFerano/rusted-nes 2025-04-16 23:46:56 +07:00
JosephFerano pushed to master at JosephFerano/gitano 2025-04-03 22:03:24 +07:00
95cb457284 Using djula templates for home and project commits
e9bcf2a941 Template files
b8cc8eaec6 Basic project setup
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JosephFerano created branch master in JosephFerano/gitano 2025-04-01 22:20:06 +07:00
JosephFerano pushed to master at JosephFerano/gitano 2025-04-01 22:20:06 +07:00
3dc33b875a List projects, list commits, wip list diff
JosephFerano created repository JosephFerano/gitano 2025-04-01 22:18:15 +07:00
JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-23 09:03:19 +07:00
85a8172923 Add .LOOP instruction, dump memory to disk with cli arg
fafb440891 Listings 54 and 55
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JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-22 18:55:27 +07:00
df105ea3cf Generalize with perform_load and perform_store, use bit_set for cpu flags
JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-22 15:22:21 +07:00
831a307975 Fix and simplify (delete) all the signage stuff
ea7b65994b Fix IN and OUT instructions decoding
ab2b107e7e Listing 53
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JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-21 20:47:59 +07:00
da78d875c1 Effective address movs work, but at what cost?
3ca4059c44 Listing 52
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JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-21 20:11:57 +07:00
11ccfe78a9 Handle Memory movs, change displacement from union to enum
948960e8f5 Listing 51
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JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-21 17:20:07 +07:00
0e90e2c23c Handle additional jumps for listing 50
JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-21 16:34:35 +07:00
99fd7fabd7 Add inst decoded type for better modeling, handle jumps correctly with IP register
d0f91f15f8 Listings 48 and 49
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JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-20 20:23:16 +07:00
731e5bd45d CF, OF, and PF flags, keep values as i16, update ref test script
JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-20 16:14:17 +07:00
5cf4768b80 Decode then check reference flags, change registers and flags to use enumerated arrays
cd5eada115 Listing 47
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JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-20 13:07:05 +07:00
08874c4533 Use an enum to represent registers, parse txt files, check CPU state against expected
JosephFerano pushed to master at JosephFerano/performance-aware 2025-03-20 09:45:08 +07:00
305ac557fa Move registers to CPU struct, start working on testing code