CF, OF, and PF flags, keep values as i16, update ref test script
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5cf4768b80
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@ -119,11 +119,11 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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if inst.has_sign_extension {
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word_signed &&= data[0] & 0b0000_0010 == 0
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}
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value: u16 = word_signed ? u16(get_i16(data[data_idx:])) : u16(data[data_idx])
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value: i16 = word_signed ? get_i16(data[data_idx:]) : i16(i8(data[data_idx]))
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operand = Immediate { value = value, size = word_signed ? .Signed16 : .Signed8 }
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processed^ += word_signed ? 2 : 1
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case .ImmediateUnsigned:
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operand = Immediate { value = u16(data[processed^]), size = .Unsigned8 }
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operand = Immediate { value = i16(data[processed^]), size = .Unsigned8 }
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processed^ += 1
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case .Accumulator:
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operand = RegisterId { name = Register(0), access = word ? .Full : .Low }
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@ -155,7 +155,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
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processed^ += 1
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case .DirectWithinSegment:
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value := (int)(get_i16(data[1:])) + CPU.total_bytes_processed + 3
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operand = Immediate { value = u16(value), size = .Signed16 }
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operand = Immediate { value = i16(value), size = .Signed16 }
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processed^ += 2
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case .Intersegment:
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operand = Intersegment {
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@ -6,30 +6,31 @@ import "core:math"
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import "core:strings"
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import "core:reflect"
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get_operand_value :: proc(operand: Operand) -> u16 {
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get_operand_value :: proc(operand: Operand) -> i16 {
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#partial switch opr in operand {
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case Immediate:
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return opr.value
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// fmt.printfln("0x%4x %d", i16(opr.value), opr.value)
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return i16(opr.value)
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case RegisterId:
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reg_val := CPU.registers[opr.name]
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switch opr.access {
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case .Low, .High:
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return u16(opr.access == .Low ? reg_val.low : reg_val.high)
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return i16(opr.access == .Low ? reg_val.low : reg_val.high)
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case .Full:
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return reg_val.full
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return i16(reg_val.full)
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}
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}
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return 0
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}
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set_register_value :: proc(reg: RegisterId, value: u16) {
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set_register_value :: proc(reg: RegisterId, value: i16) {
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switch reg.access {
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case .Low:
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CPU.registers[reg.name].low = u8(value)
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case .High:
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CPU.registers[reg.name].high = u8(value)
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case .Full:
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CPU.registers[reg.name].full = u16(value)
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CPU.registers[reg.name].full = i16(value)
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}
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}
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@ -38,12 +39,40 @@ get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
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return &cpu.registers[reg]
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}
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check_zero_flag :: proc(value: u16) {
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check_zero_flag :: proc(value: i16) {
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CPU.flags[.ZF] = value == 0
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}
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check_sign_flag :: proc(value: u16) {
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CPU.flags[.SF] = value >> 15 == 1
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check_sign_flag :: proc(value: i16) {
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CPU.flags[.SF] = (value >> 15) & 0x1 == 1
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}
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check_carry_flag :: proc(dst: i16, src: i16, is_add: bool) {
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CPU.flags[.CF] = is_add ? u32(dst) + u32(src) > 0xFFFF : src > dst
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}
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check_parity_flag :: proc(value: i16) {
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val := value
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bit_count := 0
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val &= 0x00FF
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for val != 0 {
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if val & 0x1 == 1 {
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bit_count += 1
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}
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val >>= 1
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}
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CPU.flags[.PF] = val % 2 == 0
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}
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check_auxiliary_carry_flag :: proc(dst: i16, src: i16, is_add: bool) {
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lhs, rhs := dst & 0xF, src & 0xF
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CPU.flags[.AF] = is_add ? lhs + rhs > 15 : lhs < rhs
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}
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check_flags :: proc(value: i16) {
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check_zero_flag(value)
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check_sign_flag(value)
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check_parity_flag(value)
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}
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execute_instruction :: proc(inst: Instruction) {
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@ -54,21 +83,27 @@ execute_instruction :: proc(inst: Instruction) {
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set_register_value(reg, src_val)
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case .ADD:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.name].full + src_val
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dst_val := get_operand_value(inst.dst)
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val := i16(CPU.registers[reg.name].full) + src_val
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set_register_value(reg, val)
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check_zero_flag(val)
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check_sign_flag(val)
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check_flags(val)
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check_auxiliary_carry_flag(dst_val, src_val, true)
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check_carry_flag(dst_val, src_val, true)
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case .SUB:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.name].full - src_val
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dst_val := get_operand_value(inst.dst)
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val := i16(CPU.registers[reg.name].full) - src_val
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set_register_value(reg, val)
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check_zero_flag(val)
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check_sign_flag(val)
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check_flags(val)
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check_auxiliary_carry_flag(dst_val, src_val, false)
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check_carry_flag(dst_val, src_val, false)
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case .CMP:
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src_val := get_operand_value(inst.src)
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val := CPU.registers[reg.name].full - src_val
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check_zero_flag(val)
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check_sign_flag(val)
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dst_val := get_operand_value(inst.dst)
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val := i16(CPU.registers[reg.name].full) - src_val
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check_flags(val)
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check_auxiliary_carry_flag(dst_val, src_val, false)
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check_carry_flag(dst_val, src_val, false)
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}
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}
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}
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23
sim8086.odin
23
sim8086.odin
@ -43,33 +43,40 @@ main :: proc() {
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}
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if what_to_print == "registers" || what_to_print == "all" {
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fmt.println("\nRegisters")
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fmt.println("Registers")
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for reg_val,name in CPU.registers {
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full := fmt.aprintf("%s: %d ", name, reg_val.full)
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hex := fmt.aprintf("0x%04x ", reg_val.full)
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full := fmt.aprintf("%s: %d ", name, i16(reg_val.full))
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hex := fmt.aprintf("0x%04x ", u16(reg_val.full))
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fmt.printf("%s %*[1]s %s %*[4]s %08b %08b",
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full, 18 - len(full), "|", hex, 10 - len(hex), "|", reg_val.high, reg_val.low)
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fmt.println()
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}
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fmt.println("\nFlags")
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for state,flag in CPU.flags {
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fmt.printfln("%c: %d",reflect.enum_string(flag)[0], state ? 1 : 0)
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fmt.printf("%c:%d ",reflect.enum_string(flag)[0], state ? 1 : 0)
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}
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fmt.println()
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failed_ref: bool
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path,ok := strings.replace(os.args[1], ".bin", ".txt", 1)
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ref_cpu,_ := extract_reference_cpu_state(path)
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for reg_val,name in ref_cpu.registers {
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if CPU.registers[name].full != reg_val.full {
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msg := "%s register does not match reference - Expected %04x | Actual %04x"
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fmt.eprintfln(msg, name, reg_val.full, CPU.registers[name].full)
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msg := "%s register does not match reference - Expected 0x%04x | Actual 0x%04x"
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fmt.printfln(msg, name, reg_val.full, CPU.registers[name].full)
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failed_ref = true
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}
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}
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for f in Flag {
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if ref_cpu.flags[f] != CPU.flags[f] {
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msg := "%s flag does not match reference - Expected %t | Actual %t"
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fmt.eprintfln(msg, f, ref_cpu.flags[f], CPU.flags[f])
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msg := "%s flag does not match reference - Expected %d | Actual %d"
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fmt.printfln(msg, f, ref_cpu.flags[f] ? 1 : 0, CPU.flags[f] ? 1 : 0)
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failed_ref = true
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}
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}
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if failed_ref {
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os.exit(1)
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}
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}
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if what_to_print == "instructions" || what_to_print == "all" {
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print_instructions_stdout(instructions_list[:])
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@ -16,13 +16,14 @@ odin build . -out:sim8086
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for asm_txt in asm_files/*.txt;
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do
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asm_listing=$(basename $asm_txt .txt)
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./sim8086 asm_files/${asm_listing}.bin registers | awk '{print $1 $4}' | sort > temp1
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cat $asm_txt | awk '/Final registers/,0' | tail -n +2 | awk '{print $1 $2}' | sort > temp2
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diff -U0 --color temp1 temp2
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output=$(./sim8086 asm_files/${asm_listing}.bin registers)
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if [ $? -eq 1 ]; then
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echo Listing $asm_listing Failed!
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echo -e "Listing $asm_listing ${RED}Failed!${NC}"
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echo "$output" | while IFS= read -r line; do
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echo "$line"
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done
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echo -e ""
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else
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echo Listing $asm_listing Succeded!
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echo -e "Listing $asm_listing: ${GREEN}Succeded!${NC}"
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fi
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done
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rm temp1 temp2
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@ -44,7 +44,7 @@ extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
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reg_value := get_cpu_register_by_name(&cpu, reg_name)
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hex_string := line[i+6:i+10]
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if hex_num,ok := strconv.parse_int(hex_string, 16); ok {
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reg_value^.full = u16(hex_num)
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reg_value^.full = i16(hex_num)
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}
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}
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break
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@ -19,7 +19,7 @@ RegisterValue :: struct #raw_union {
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using _: struct {
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low, high: byte,
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},
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full: u16,
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full: i16,
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}
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Flag :: enum {
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@ -69,7 +69,7 @@ ImmediateSize :: enum {
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Signed16,
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}
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Immediate :: struct {
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value: u16,
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value: i16,
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size: ImmediateSize,
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}
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MemoryAddr :: struct {
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