Process mov instruction properly, 01-02-39.asm now decoded properly
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parent
c5e9cfac44
commit
fbedf7cf67
125
decoder8086.odin
125
decoder8086.odin
@ -51,6 +51,34 @@ instructions := [?]Instruction {
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}
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}
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inst_map := make(map[u8]Instruction)
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inst_map := make(map[u8]Instruction)
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RIGHT_ALIGN_AMOUNT := 30
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get_instruction :: proc(bytes: []u8) -> (Instruction, u8) {
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return {}, 0
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}
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calculate_effective_address :: proc(r_m: u8) -> string {
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val: string
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switch r_m {
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case 0b000:
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val = "bx + si"
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case 0b001:
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val = "bx + di"
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case 0b010:
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val = "bp + si"
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case 0b011:
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val = "bp + di"
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case 0b100:
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val = "si"
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case 0b101:
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val = "di"
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case 0b110:
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val = "bp"
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case 0b111:
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val = "bx"
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}
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return val
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}
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main :: proc() {
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main :: proc() {
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ax := registers[0]
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ax := registers[0]
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@ -72,48 +100,89 @@ main :: proc() {
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inst_map[inst.encoding] = inst
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inst_map[inst.encoding] = inst
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}
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}
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if true {
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if false {
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for i in 0..<bytes_read {
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for i in 0..<bytes_read {
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fmt.printfln("%b", data[i])
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fmt.printfln("Checking %b:", data[i])
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mask: u8 = 0b11111111
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mask: u8 = 0xFF
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for i in 0..=4 {
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for j in 0..=4 {
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encoding := data[i] & mask
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encoding := data[i] & mask
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fmt.printfln("\tNext: %b %b", data[i], encoding)
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if inst, ok := inst_map[encoding]; ok {
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if inst, ok := inst_map[encoding]; ok {
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fmt.printfln("%b, %v", encoding, inst.desc)
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fmt.printfln("\t%b, %v", encoding, inst.desc)
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// fmt.println(inst.desc)
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break
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break
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}
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}
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mask <<= 1
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mask <<= 1
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}
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}
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// fmt.println("=============")
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}
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}
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os.exit(0)
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os.exit(0)
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}
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}
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read_next := false
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read_next := false
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src_dst := true
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src_dst := true
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is_word := false
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prev :u8 = 0
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fmt.println("bits 16\n")
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fmt.println("bits 16\n")
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for i in 0..<bytes_read {
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processed := 0
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b := data[i]
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for processed < bytes_read {
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if read_next {
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curr_byte := data[processed]
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mod := (b & 0b11000000) >> 6
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if curr_byte & 0b11111000 == 0b10001000 {
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reg := (b & 0b00111000) >> 3
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is_word := curr_byte & 1 == 1
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rm := b & 0b00000111
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flip_src := curr_byte & 2 != 0
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src_name := is_word ? registers[reg].fullname : registers[reg].bytename
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disp_amount := 0
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dst_name := is_word ? registers[rm].fullname : registers[rm].bytename
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fmt.printfln("mov %s, %s ;; %b %b", dst_name, src_name, prev, b)
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next_byte := data[processed + 1]
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read_next = false
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mod := (next_byte & 0b11000000) >> 6
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continue
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reg := (next_byte & 0b00111000) >> 3
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rm := next_byte & 0b00000111
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dst_reg := registers[rm]
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disp: string
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if mod == 1 {
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disp_byte := (i16)(data[processed + 2])
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disp_amount = 1
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disp = disp_byte == 0 ? "" : fmt.aprintf(" + %d", disp_byte)
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} else if mod == 2 {
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disp_byte := (i16)(data[processed + 3]) << 8 | (i16)(data[processed + 2])
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disp_amount = 2
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disp = disp_byte == 0 ? "" : fmt.aprintf(" + %d", disp_byte)
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} else {
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disp = ""
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}
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src_name: string
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if mod == 3 {
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// Register-to-register
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src_name = is_word ? registers[rm].fullname : registers[rm].bytename
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} else {
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src_name = fmt.aprintf("[%s%s]", calculate_effective_address(rm), disp)
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}
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dst_name := is_word ? registers[reg].fullname : registers[reg].bytename
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if flip_src { src_name, dst_name = dst_name, src_name }
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processed += 1 + ((int)(mod) % 3)
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inst_string := fmt.aprintf("mov %s, %s", src_name, dst_name)
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fmt.printfln("%s %*[1]s %08b %08b", inst_string, RIGHT_ALIGN_AMOUNT - len(inst_string), ";; 1", curr_byte, next_byte)
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} else if curr_byte & 0b1111_0000 == 0b10110000 {
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is_word := curr_byte & 0b0000_1000 != 0
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reg := curr_byte & 0b00000111
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dst_name: string
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imm: i16
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if is_word {
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dst_name = registers[reg].fullname
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imm = (i16)(data[processed+2]) << 8 | (i16)(data[processed+1])
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processed += 2
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} else {
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dst_name = registers[reg].bytename
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imm = (i16)(data[processed+1])
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processed += 1
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}
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inst_string := fmt.aprintf("mov %s, %d", dst_name, imm)
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fmt.printfln("%s %*[1]s %08b %08b", inst_string, RIGHT_ALIGN_AMOUNT - len(inst_string), ";; 2", curr_byte, data[processed + 1])
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} else {
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fmt.printfln("unknown instruction ;; %b", curr_byte)
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}
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}
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if b == 0b10001001 {
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processed += 1
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read_next = true
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is_word = true
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} else if b == 0b10001000 {
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read_next = true
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is_word = false
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}
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prev = b
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}
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}
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}
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}
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