Listings 0056, 0057. Improve README

.gitignore

@@ -5,3 +5,4 @@
 /decoder8086
 /performance-aware
 /sim8086
+/listing-*.data

README.org

@@ -1,8 +1,96 @@
 #+OPTIONS: toc:nil
 
-* 8086 CPU Emulator
+* 8086 CPU Simulator
-Following along with [[https://www.computerenhance.com/p/table-of-contents][Performance Aware by Computer Enhance]]
+
-* License
+A complete 8086 processor emulator written in Odin, featuring instruction decoding, execution, and cycle-accurate simulation. Implements a comprehensive subset of the Intel 8086 instruction set with proper flag handling, memory management, and register operations.
-This project is licensed under the terms of the MIT license. For more
+
-information, see the included LICENSE file. However, some of this is related to
+** Features
-a paid course so maybe pay for the course if you want to use these files?
+
+- *Complete 8086 instruction decoding* - Supports MOV, arithmetic, jumps, loops, stack operations, and more
+- *Cycle-accurate execution* - Proper CPU state management with registers and flags
+- *Memory simulation* - 1MB addressable memory space with effective address calculation
+- *Comprehensive testing* - 21 assembly test programs with automated validation
+- *Reference validation* - Compares execution results against reference CPU states
+
+** Architecture
+
+The simulator is organized into several focused modules:
+
+- =sim8086.odin= - Main entry point and program orchestration
+- =types.odin= - Core data structures (CPU state, instructions, operands)
+- =instructions.odin= - Complete 8086 instruction set definitions
+- =decoding.odin= - Binary instruction decoding and parsing
+- =execution.odin= - CPU execution engine with flag calculations
+- =printing.odin= - Assembly output formatting
+- =testing.odin= - Reference state parsing and validation
+
+** Building and Running
+
+#+BEGIN_SRC bash
+# Build the simulator
+make
+
+# Decode and print assembly
+./sim8086 program.bin instructions
+
+# Execute with register dump
+./sim8086 program.bin registers
+
+# Full execution with memory dump
+./sim8086 program.bin all dump
+#+END_SRC
+
+** Testing
+
+Comprehensive test coverage included:
+
+#+BEGIN_SRC bash
+# Run all assembly tests
+./test_asm.sh
+
+# Run reference CPU validation tests
+./test_ref_cpu.sh
+#+END_SRC
+
+Test files cover:
+- Basic MOV operations and addressing modes
+- Arithmetic and logical operations with proper flag setting
+- Jump and loop instructions
+- Stack operations (PUSH/POP)
+- Complex programs with multiple instruction types
+
+** Technical Implementation
+
+*** Instruction Decoding
+- Bit-level parsing of 8086 machine code
+- Support for all addressing modes (register, immediate, memory, direct)
+- Proper handling of prefixes and multi-byte instructions
+
+*** Execution Engine
+- Register file with proper 8/16-bit access patterns
+- CPU flags (Zero, Carry, Sign, Overflow, etc.) with accurate calculations
+- Effective address computation for memory operations
+- Instruction pointer management and control flow
+
+*** Memory Model
+- 1MB linear address space
+- Little-endian byte ordering
+- Memory-mapped I/O simulation
+
+** Supported Instructions
+
+*Data Movement:* MOV, PUSH, POP, XCHG, LEA, LDS, LES
+*Arithmetic:* ADD, SUB, MUL, DIV, INC, DEC, CMP, NEG
+*Logical:* AND, OR, XOR, NOT, TEST
+*Shifts/Rotates:* SHL, SHR, SAR, ROL, ROR, RCL, RCR
+*Control Flow:* JMP, JE, JNE, JL, JG, LOOP, CALL, RET
+*String Operations:* MOVS, CMPS, SCAS, LODS, STOS
+*System:* INT, IRET, HLT, NOP
+
+Built following the [[https://www.computerenhance.com/p/table-of-contents][Performance Aware Programming]] course by Casey Muratori.
+
+** License
+
+This project is licensed under the MIT License - see the LICENSE file for details.
+
+*Note:* Some test files are derived from the Performance Aware Programming course materials. Consider supporting the course if you find this project useful.

asm_files/list-0053.asm

@@ -0,0 +1,35 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 53
+; ========================================================================
+
+bits 16
+
+mov dx, 6
+mov bp, 1000
+
+mov si, 0
+init_loop_start:
+	mov word [bp + si], si
+	add si, 2
+	cmp si, dx
+	jnz init_loop_start
+
+mov bx, 0
+mov si, dx
+sub bp, 2
+add_loop_start:
+	add bx, word [bp + si]
+	sub si, 2
+	jnz add_loop_start

asm_files/list-0053.txt

@@ -0,0 +1,35 @@
+--- test\listing_0053_add_loop_challenge execution ---
+mov dx, 6 ; dx:0x0->0x6 ip:0x0->0x3 
+mov bp, 1000 ; bp:0x0->0x3e8 ip:0x3->0x6 
+mov si, 0 ; ip:0x6->0x9 
+mov word [bp+si], si ; ip:0x9->0xb 
+add si, 2 ; si:0x0->0x2 ip:0xb->0xe 
+cmp si, dx ; ip:0xe->0x10 flags:->CPAS 
+jne $-7 ; ip:0x10->0x9 
+mov word [bp+si], si ; ip:0x9->0xb 
+add si, 2 ; si:0x2->0x4 ip:0xb->0xe flags:CPAS-> 
+cmp si, dx ; ip:0xe->0x10 flags:->CAS 
+jne $-7 ; ip:0x10->0x9 
+mov word [bp+si], si ; ip:0x9->0xb 
+add si, 2 ; si:0x4->0x6 ip:0xb->0xe flags:CAS->P 
+cmp si, dx ; ip:0xe->0x10 flags:P->PZ 
+jne $-7 ; ip:0x10->0x12 
+mov bx, 0 ; ip:0x12->0x15 
+mov si, dx ; ip:0x15->0x17 
+sub bp, 2 ; bp:0x3e8->0x3e6 ip:0x17->0x1a flags:PZ-> 
+add bx, [bp+si] ; bx:0x0->0x4 ip:0x1a->0x1c 
+sub si, 2 ; si:0x6->0x4 ip:0x1c->0x1f 
+jne $-5 ; ip:0x1f->0x1a 
+add bx, [bp+si] ; bx:0x4->0x6 ip:0x1a->0x1c flags:->P 
+sub si, 2 ; si:0x4->0x2 ip:0x1c->0x1f flags:P-> 
+jne $-5 ; ip:0x1f->0x1a 
+add bx, [bp+si] ; ip:0x1a->0x1c flags:->P 
+sub si, 2 ; si:0x2->0x0 ip:0x1c->0x1f flags:P->PZ 
+jne $-5 ; ip:0x1f->0x21 
+
+Final registers:
+      bx: 0x0006 (6)
+      dx: 0x0006 (6)
+      bp: 0x03e6 (998)
+      ip: 0x0021 (33)
+   flags: PZ

asm_files/list-0054.asm

@@ -0,0 +1,43 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 54
+; ========================================================================
+
+bits 16
+
+; Start image after one row, to avoid overwriting our code!
+mov bp, 64*4
+
+mov dx, 0
+y_loop_start:
+	
+	mov cx, 0
+	x_loop_start:
+		; Fill pixel
+		mov word [bp + 0], cx ; Red
+		mov word [bp + 2], dx ; Blue
+		mov byte [bp + 3], 255 ; Alpha
+			
+		; Advance pixel location
+		add bp, 4
+			
+		; Advance X coordinate and loop
+		add cx, 1
+		cmp cx, 64
+		jnz x_loop_start
+	
+	; Advance Y coordinate and loop
+	add dx, 1
+	cmp dx, 64
+	jnz y_loop_start

asm_files/list-0055.asm

@@ -0,0 +1,53 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 55
+; ========================================================================
+
+bits 16
+
+; Start image after one row, to avoid overwriting our code!
+mov bp, 64*4
+
+; Draw the solid rectangle red/blue/alpha
+mov dx, 64
+y_loop_start:
+	
+	mov cx, 64
+	x_loop_start:
+		mov byte [bp + 0], cl  ; Red
+		mov byte [bp + 1], 0   ; Green
+		mov byte [bp + 2], dl  ; Blue
+		mov byte [bp + 3], 255 ; Alpha
+		add bp, 4
+			
+		loop x_loop_start
+	
+	sub dx, 1
+	jnz y_loop_start
+
+; Add the line rectangle green
+mov bp, 64*4 + 4*64 + 4
+mov bx, bp
+mov cx, 62
+outline_loop_start:
+	
+	mov byte [bp + 1], 255 ; Top line
+	mov byte [bp + 61*64*4 + 1], 255 ; Bottom line
+	mov byte [bx + 1], 255 ; Left line
+	mov byte [bx + 61*4 + 1], 255 ; Right  line
+	
+	add bp, 4
+	add bx, 4*64
+			
+	loop outline_loop_start

asm_files/list-0056.asm

@@ -0,0 +1,41 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 56
+; ========================================================================
+
+bits 16
+
+mov bx, 1000
+mov bp, 2000
+mov si, 3000
+mov di, 4000
+
+mov cx, bx
+mov dx, 12
+
+mov dx, [1000]
+
+mov cx, [bx]
+mov cx, [bp]
+mov [si], cx
+mov [di], cx 
+
+mov cx, [bx + 1000]
+mov cx, [bp + 1000]
+mov [si + 1000], cx 
+mov [di + 1000], cx
+
+add cx, dx
+add [di + 1000], cx
+add dx, 50

asm_files/list-0056.txt

@@ -0,0 +1,72 @@
+**************
+**** 8086 ****
+**************
+
+WARNING: Clocks reported by this utility are strictly from the 8086 manual.
+They will be inaccurate, both because the manual clocks are estimates, and because
+some of the entries in the manual look highly suspicious and are probably typos.
+
+--- test\listing_0056_estimating_cycles execution ---
+mov bx, 1000 ; Clocks: +4 = 4 | bx:0x0->0x3e8 ip:0x0->0x3 
+mov bp, 2000 ; Clocks: +4 = 8 | bp:0x0->0x7d0 ip:0x3->0x6 
+mov si, 3000 ; Clocks: +4 = 12 | si:0x0->0xbb8 ip:0x6->0x9 
+mov di, 4000 ; Clocks: +4 = 16 | di:0x0->0xfa0 ip:0x9->0xc 
+mov cx, bx ; Clocks: +2 = 18 | cx:0x0->0x3e8 ip:0xc->0xe 
+mov dx, 12 ; Clocks: +4 = 22 | dx:0x0->0xc ip:0xe->0x11 
+mov dx, [+1000] ; Clocks: +14 = 36 (8 + 6ea) | dx:0xc->0x0 ip:0x11->0x15 
+mov cx, [bx] ; Clocks: +13 = 49 (8 + 5ea) | cx:0x3e8->0x0 ip:0x15->0x17 
+mov cx, [bp] ; Clocks: +13 = 62 (8 + 5ea) | ip:0x17->0x1a 
+mov word [si], cx ; Clocks: +14 = 76 (9 + 5ea) | ip:0x1a->0x1c 
+mov word [di], cx ; Clocks: +14 = 90 (9 + 5ea) | ip:0x1c->0x1e 
+mov cx, [bx+1000] ; Clocks: +17 = 107 (8 + 9ea) | ip:0x1e->0x22 
+mov cx, [bp+1000] ; Clocks: +17 = 124 (8 + 9ea) | ip:0x22->0x26 
+mov word [si+1000], cx ; Clocks: +18 = 142 (9 + 9ea) | ip:0x26->0x2a 
+mov word [di+1000], cx ; Clocks: +18 = 160 (9 + 9ea) | ip:0x2a->0x2e 
+add cx, dx ; Clocks: +3 = 163 | ip:0x2e->0x30 flags:->PZ 
+add word [di+1000], cx ; Clocks: +25 = 188 (16 + 9ea) | ip:0x30->0x34 
+add dx, 50 ; Clocks: +4 = 192 | dx:0x0->0x32 ip:0x34->0x37 flags:PZ-> 
+
+Final registers:
+      bx: 0x03e8 (1000)
+      dx: 0x0032 (50)
+      bp: 0x07d0 (2000)
+      si: 0x0bb8 (3000)
+      di: 0x0fa0 (4000)
+      ip: 0x0037 (55)
+
+
+**************
+**** 8088 ****
+**************
+
+WARNING: Clocks reported by this utility are strictly from the 8086 manual.
+They will be inaccurate, both because the manual clocks are estimates, and because
+some of the entries in the manual look highly suspicious and are probably typos.
+
+--- test\listing_0056_estimating_cycles execution ---
+mov bx, 1000 ; Clocks: +4 = 4 | bx:0x0->0x3e8 ip:0x0->0x3
+mov bp, 2000 ; Clocks: +4 = 8 | bp:0x0->0x7d0 ip:0x3->0x6
+mov si, 3000 ; Clocks: +4 = 12 | si:0x0->0xbb8 ip:0x6->0x9
+mov di, 4000 ; Clocks: +4 = 16 | di:0x0->0xfa0 ip:0x9->0xc
+mov cx, bx ; Clocks: +2 = 18 | cx:0x0->0x3e8 ip:0xc->0xe
+mov dx, 12 ; Clocks: +4 = 22 | dx:0x0->0xc ip:0xe->0x11
+mov dx, [+1000] ; Clocks: +18 = 40 (8 + 6ea + 4p) | dx:0xc->0x0 ip:0x11->0x15
+mov cx, [bx] ; Clocks: +17 = 57 (8 + 5ea + 4p) | cx:0x3e8->0x0 ip:0x15->0x17
+mov cx, [bp] ; Clocks: +17 = 74 (8 + 5ea + 4p) | ip:0x17->0x1a
+mov word [si], cx ; Clocks: +18 = 92 (9 + 5ea + 4p) | ip:0x1a->0x1c
+mov word [di], cx ; Clocks: +18 = 110 (9 + 5ea + 4p) | ip:0x1c->0x1e
+mov cx, [bx+1000] ; Clocks: +21 = 131 (8 + 9ea + 4p) | ip:0x1e->0x22
+mov cx, [bp+1000] ; Clocks: +21 = 152 (8 + 9ea + 4p) | ip:0x22->0x26
+mov word [si+1000], cx ; Clocks: +22 = 174 (9 + 9ea + 4p) | ip:0x26->0x2a
+mov word [di+1000], cx ; Clocks: +22 = 196 (9 + 9ea + 4p) | ip:0x2a->0x2e
+add cx, dx ; Clocks: +3 = 199 | ip:0x2e->0x30 flags:->PZ
+add word [di+1000], cx ; Clocks: +33 = 232 (16 + 9ea + 8p) | ip:0x30->0x34
+add dx, 50 ; Clocks: +4 = 236 | dx:0x0->0x32 ip:0x34->0x37 flags:PZ->
+
+Final registers:
+      bx: 0x03e8 (1000)
+      dx: 0x0032 (50)
+      bp: 0x07d0 (2000)
+      si: 0x0bb8 (3000)
+      di: 0x0fa0 (4000)
+      ip: 0x0037 (55)

asm_files/list-0057.asm

@@ -0,0 +1,42 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 57
+; ========================================================================
+
+bits 16
+
+mov bx, 1000
+mov bp, 2000
+mov si, 3000
+mov di, 4000
+
+mov cx, [bp + di]
+mov [bx + si], cx
+
+mov cx, [bp + si]
+mov [bx + di], cx
+
+mov cx, [bp + di + 1000]
+mov [bx + si + 1000], cx
+
+mov cx, [bp + si + 1000]
+mov [bx + di + 1000], cx
+
+add dx, [bp + si + 1000]
+
+add word [bp + si], 76
+
+add dx, [bp + si + 1001]
+add [di + 999], dx
+add word [bp + si], 75

asm_files/list-0057.txt

@@ -0,0 +1,71 @@
+**************
+**** 8086 ****
+**************
+
+WARNING: Clocks reported by this utility are strictly from the 8086 manual.
+They will be inaccurate, both because the manual clocks are estimates, and because
+some of the entries in the manual look highly suspicious and are probably typos.
+
+--- test\listing_0057_challenge_cycles execution ---
+mov bx, 1000 ; Clocks: +4 = 4 | bx:0x0->0x3e8 ip:0x0->0x3 
+mov bp, 2000 ; Clocks: +4 = 8 | bp:0x0->0x7d0 ip:0x3->0x6 
+mov si, 3000 ; Clocks: +4 = 12 | si:0x0->0xbb8 ip:0x6->0x9 
+mov di, 4000 ; Clocks: +4 = 16 | di:0x0->0xfa0 ip:0x9->0xc 
+mov cx, [bp+di] ; Clocks: +15 = 31 (8 + 7ea) | ip:0xc->0xe 
+mov word [bx+si], cx ; Clocks: +16 = 47 (9 + 7ea) | ip:0xe->0x10 
+mov cx, [bp+si] ; Clocks: +16 = 63 (8 + 8ea) | ip:0x10->0x12 
+mov word [bx+di], cx ; Clocks: +17 = 80 (9 + 8ea) | ip:0x12->0x14 
+mov cx, [bp+di+1000] ; Clocks: +19 = 99 (8 + 11ea) | ip:0x14->0x18 
+mov word [bx+si+1000], cx ; Clocks: +20 = 119 (9 + 11ea) | ip:0x18->0x1c 
+mov cx, [bp+si+1000] ; Clocks: +20 = 139 (8 + 12ea) | ip:0x1c->0x20 
+mov word [bx+di+1000], cx ; Clocks: +21 = 160 (9 + 12ea) | ip:0x20->0x24 
+add dx, [bp+si+1000] ; Clocks: +21 = 181 (9 + 12ea) | ip:0x24->0x28 flags:->PZ 
+add word [bp+si], 76 ; Clocks: +25 = 206 (17 + 8ea) | ip:0x28->0x2b flags:PZ-> 
+add dx, [bp+si+1001] ; Clocks: +25 = 231 (9 + 12ea + 4p) | ip:0x2b->0x2f flags:->PZ 
+add word [di+999], dx ; Clocks: +33 = 264 (16 + 9ea + 8p) | ip:0x2f->0x33 flags:PZ->P 
+add word [bp+si], 75 ; Clocks: +25 = 289 (17 + 8ea) | ip:0x33->0x36 flags:P->A 
+
+Final registers:
+      bx: 0x03e8 (1000)
+      bp: 0x07d0 (2000)
+      si: 0x0bb8 (3000)
+      di: 0x0fa0 (4000)
+      ip: 0x0036 (54)
+   flags: A
+
+
+
+**************
+**** 8088 ****
+**************
+
+WARNING: Clocks reported by this utility are strictly from the 8086 manual.
+They will be inaccurate, both because the manual clocks are estimates, and because
+some of the entries in the manual look highly suspicious and are probably typos.
+
+--- test\listing_0057_challenge_cycles execution ---
+mov bx, 1000 ; Clocks: +4 = 4 | bx:0x0->0x3e8 ip:0x0->0x3
+mov bp, 2000 ; Clocks: +4 = 8 | bp:0x0->0x7d0 ip:0x3->0x6
+mov si, 3000 ; Clocks: +4 = 12 | si:0x0->0xbb8 ip:0x6->0x9
+mov di, 4000 ; Clocks: +4 = 16 | di:0x0->0xfa0 ip:0x9->0xc
+mov cx, [bp+di] ; Clocks: +19 = 35 (8 + 7ea + 4p) | ip:0xc->0xe
+mov word [bx+si], cx ; Clocks: +20 = 55 (9 + 7ea + 4p) | ip:0xe->0x10
+mov cx, [bp+si] ; Clocks: +20 = 75 (8 + 8ea + 4p) | ip:0x10->0x12
+mov word [bx+di], cx ; Clocks: +21 = 96 (9 + 8ea + 4p) | ip:0x12->0x14
+mov cx, [bp+di+1000] ; Clocks: +23 = 119 (8 + 11ea + 4p) | ip:0x14->0x18
+mov word [bx+si+1000], cx ; Clocks: +24 = 143 (9 + 11ea + 4p) | ip:0x18->0x1c
+mov cx, [bp+si+1000] ; Clocks: +24 = 167 (8 + 12ea + 4p) | ip:0x1c->0x20
+mov word [bx+di+1000], cx ; Clocks: +25 = 192 (9 + 12ea + 4p) | ip:0x20->0x24
+add dx, [bp+si+1000] ; Clocks: +25 = 217 (9 + 12ea + 4p) | ip:0x24->0x28 flags:->PZ
+add word [bp+si], 76 ; Clocks: +33 = 250 (17 + 8ea + 8p) | ip:0x28->0x2b flags:PZ->
+add dx, [bp+si+1001] ; Clocks: +25 = 275 (9 + 12ea + 4p) | ip:0x2b->0x2f flags:->PZ
+add word [di+999], dx ; Clocks: +33 = 308 (16 + 9ea + 8p) | ip:0x2f->0x33 flags:PZ->P
+add word [bp+si], 75 ; Clocks: +33 = 341 (17 + 8ea + 8p) | ip:0x33->0x36 flags:P->A
+
+Final registers:
+      bx: 0x03e8 (1000)
+      bp: 0x07d0 (2000)
+      si: 0x0bb8 (3000)
+      di: 0x0fa0 (4000)
+      ip: 0x0036 (54)
+   flags: A

decoding.odin

@@ -102,10 +102,13 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
                 op = MemoryAddr{ addr_id = rm }
             }
         } else if mod == 1 {
-            op = MemoryAddr{ addr_id = rm , displacement_value = (i16)(data[2]) , displacement_size = .Signed8 }
+            // NOTE: Per the 8086 manual in order to detect signed displacement, you have
+            // to sign extend a byte to a word. In Odin like in other languages, first
+            // cast to an i8, before casting to an i16 and it'll sign extend
+            op = MemoryAddr{ addr_id = rm , displacement = i16(i8(data[2])) }
             processed^ += 1
         } else if mod == 2 {
-            op = MemoryAddr{ addr_id = rm , displacement_value = get_i16(data[2:]) , displacement_size = .Signed16 }
+            op = MemoryAddr{ addr_id = rm , displacement = get_i16(data[2:]) }
             processed^ += 2
         } else if mod == 3 {
             if word {
@@ -122,13 +125,10 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
             word_signed &&= data[0] & 0b0000_0010 == 0
         }
         value: i16 = word_signed ? get_i16(data[data_idx:]) : i16(i8(data[data_idx]))
-        operand = Immediate { value = value, size = word_signed ? .Signed16 : .Signed8 }
+        operand = Immediate { value = value, size = word_signed ? ._16 : ._8 }
         processed^ += word_signed ? 2 : 1
-    case .ImmediateUnsigned:
-        operand = Immediate { value = i16(data[processed^]), size = .Unsigned8 }
-        processed^ += 1
     case .Accumulator:
-        operand = RegisterId { name = Register(0), access = word ? .Full : .Low }
+        operand = RegisterId { name = .ax, access = word ? .Full : .Low }
     case .DirectAddress:
         // operand = DirectAddress { value = get_i16(data[1:]) }
         operand = (DirectAddress)(get_i16(data[1:]))
@@ -138,10 +138,17 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
         // NOTE: In order to mimic the label offset, you have to take the value you got and add two
         operand = (Jump)((i8)(data[1]) + 2)
     case .VariablePort:
-        operand = RegisterId { name = Register.dx, access = .Full }
+        // NOTE: This isn't documented in the manual, but you can tell if we need to use
+        // the dx register or an immediate if the 4th LSB bit is set
+        if (data[0] & 0b1000) >> 3 == 1 {
+            operand = RegisterId { name = .dx, access = .Full }
+        } else {
+            operand = Immediate { value = i16(i8(data[1])), size = ._8 }
+            processed^ += 1
+        }
     case .ShiftRotate:
         v_flag := data[0] & 0b10 != 0
-        operand = v_flag ? RegisterId { name = Register(1), access = .Low } : Immediate { value = 1 }
+        operand = v_flag ? RegisterId { name = .cx, access = .Low } : Immediate { value = 1 }
     case .Repeat:
         bits := (data[1] & 0b1110) >> 1
         w := (data[1] & 0b1) == 1 ? "w" : "b"
@@ -157,7 +164,7 @@ parse_operand :: proc(inst: InstructionInfo, opinfo: OperandInfo, data: []u8, pr
         processed^ += 1
     case .DirectWithinSegment:
         value := (int)(get_i16(data[1:])) + total_bytes_processed + 3
-        operand = Immediate { value = i16(value), size = .Signed16 }
+        operand = Immediate { value = i16(value), size = ._16 }
         processed^ += 2
     case .Intersegment:
         operand = Intersegment {

execution.odin

@@ -5,6 +5,7 @@ import "core:fmt"
 import "core:math"
 import "core:strings"
 import "core:reflect"
+import "core:strconv"
 
 get_ip :: proc(cpu: ^Cpu) -> int { return int(cpu.registers[.ip].full) }
 
@@ -22,7 +23,7 @@ get_effective_address_value :: proc(cpu: ^Cpu, id: u8) -> i16 {
     return -1
 }
 
-get_operand_value :: proc(cpu: ^Cpu, operand: Operand) -> i16 {
+perform_load :: proc(cpu: ^Cpu, operand: Operand, is_word: bool) -> i16 {
     #partial switch opr in operand {
     case Immediate:
         return i16(opr.value)
@@ -35,51 +36,38 @@ get_operand_value :: proc(cpu: ^Cpu, operand: Operand) -> i16 {
             return i16(reg_val.full)
         }
     case DirectAddress:
-        value := i16(u16(cpu.memory[opr+1] << 8) | u16(cpu.memory[opr]))
+        value: i16
+        if is_word {
+            value = i16(u16(cpu.memory[opr+1] << 8) | u16(cpu.memory[opr]))
+        } else {
+            value = i16(cpu.memory[opr])
+        }
         return value
     case MemoryAddr:
-        idx := get_effective_address_value(cpu, opr.addr_id) + opr.displacement_value
+        value: i16
-        value := i16(u16(cpu.memory[idx+1] << 8) | u16(cpu.memory[idx]))
+        idx := get_effective_address_value(cpu, opr.addr_id) + opr.displacement
-        // fmt.println("Checking", idx)
+        if is_word {
-        // for i in 0..<6 {
+            value = i16(u16(cpu.memory[idx+1] << 8) | u16(cpu.memory[idx]))
-        //     fmt.printf("%04x ", cpu.memory[int(idx)-3+i])
+        } else {
-        // }
+            value = i16(cpu.memory[idx])
-        // fmt.println()
+        }
         return value
     }
     return 0
 }
 
-set_register_value :: proc(cpu: ^Cpu, reg: RegisterId, value: i16) {
+check_flags :: proc(cpu: ^Cpu, flags: bit_set[Flag], dst: i16, src: i16, result: i16, is_add: bool) {
-    switch reg.access {
+    if .ZF in flags do cpu.flags[.ZF] = result == 0
-    case .Low:
+    if .SF in flags do cpu.flags[.SF] = (result >> 15) & 0x1 == 1
-        cpu.registers[reg.name].low = u8(value)
+    if .CF in flags {
-    case .High:
-        cpu.registers[reg.name].high = u8(value)
-    case .Full:
-        cpu.registers[reg.name].full = i16(value)
-    }
-}
-
-get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
-    reg,_ := reflect.enum_from_name(Register, name)
-    return &cpu.registers[reg]
-}
-
-check_zero_flag :: proc(cpu: ^Cpu, value: i16) {
-    cpu.flags[.ZF] = value == 0
-}
-
-check_sign_flag :: proc(cpu: ^Cpu, value: i16) {
-    cpu.flags[.SF] = (value >> 15) & 0x1 == 1
-}
-
-check_carry_flag :: proc(cpu: ^Cpu, dst: i16, src: i16, is_add: bool) {
         cpu.flags[.CF] = is_add ? u32(dst) + u32(src) > 0xFFFF : src > dst
-}
+    }
-
+    if .AF in flags {
-check_parity_flag :: proc(cpu: ^Cpu, value: i16) {
+        lhs, rhs := dst & 0xF, src & 0xF
-    val := value
+        cpu.flags[.AF] = is_add ? lhs + rhs > 15 : lhs < rhs
+    }
+    if .PF in flags {
+        val := result
         bit_count := 0
         val &= 0x00FF
         for val != 0 {
@@ -89,85 +77,33 @@ check_parity_flag :: proc(cpu: ^Cpu, value: i16) {
             val >>= 1
         }
         cpu.flags[.PF] = bit_count % 2 == 0
+    }
 }
 
-check_auxiliary_carry_flag :: proc(cpu: ^Cpu, dst: i16, src: i16, is_add: bool) {
+perform_store :: proc(cpu: ^Cpu, value: i16, operand: Operand, is_word: bool) {
-    lhs, rhs := dst & 0xF, src & 0xF
+    #partial switch opr in operand {
-    cpu.flags[.AF] = is_add ? lhs + rhs > 15 : lhs < rhs
+    case RegisterId:
-}
+        switch opr.access {
-
+        case .Low:
-check_flags :: proc(cpu: ^Cpu, value: i16) {
+            cpu.registers[opr.name].low = u8(value)
-    check_zero_flag(cpu, value)
+        case .High:
-    check_sign_flag(cpu, value)
+            cpu.registers[opr.name].high = u8(value)
-    check_parity_flag(cpu, value)
+        case .Full:
+            cpu.registers[opr.name].full = i16(value)
+        }
+    case DirectAddress:
+        cpu.memory[opr] = u8(value)
+        if is_word do cpu.memory[opr+1] = u8((u16(value) & 0xFF00) >> 8)
+    case MemoryAddr:
+        effective_addr_val := get_effective_address_value(cpu, opr.addr_id)
+        addr := effective_addr_val + opr.displacement
+        cpu.memory[addr] = u8(value)
+        if is_word do cpu.memory[addr+1] = u8((u16(value) & 0xFF00) >> 8)
+    }
 }
 
 execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
-    if reg,ok := inst.dst.(RegisterId); ok {
+    if jmp_offset,ok := inst.src.(Jump); ok {
-        #partial switch inst.opname {
-        case .MOV:
-            src_val := get_operand_value(cpu, inst.src)
-            set_register_value(cpu, reg, src_val)
-        case .ADD:
-            src_val := get_operand_value(cpu, inst.src)
-            dst_val := get_operand_value(cpu, inst.dst)
-            val := i16(cpu.registers[reg.name].full) + src_val
-            set_register_value(cpu, reg, val)
-            check_flags(cpu, val)
-            check_auxiliary_carry_flag(cpu, dst_val, src_val, true)
-            check_carry_flag(cpu, dst_val, src_val, true)
-        case .SUB:
-            src_val := get_operand_value(cpu, inst.src)
-            dst_val := get_operand_value(cpu, inst.dst)
-            val := i16(cpu.registers[reg.name].full) - src_val
-            set_register_value(cpu, reg, val)
-            check_flags(cpu, val)
-            check_auxiliary_carry_flag(cpu, dst_val, src_val, false)
-            check_carry_flag(cpu, dst_val, src_val, false)
-        case .CMP:
-            src_val := get_operand_value(cpu, inst.src)
-            dst_val := get_operand_value(cpu, inst.dst)
-            val := i16(cpu.registers[reg.name].full) - src_val
-            check_flags(cpu, val)
-            check_auxiliary_carry_flag(cpu, dst_val, src_val, false)
-            check_carry_flag(cpu, dst_val, src_val, false)
-        }
-    } else if addr,ok := inst.dst.(DirectAddress); ok {
-        #partial switch inst.opname {
-        case .MOV:
-            if imm,ok := inst.src.(Immediate); ok {
-                if imm.size == .Signed16 {
-                    cpu.memory[addr]   = u8(imm.value & 0x00FF)
-                    cpu.memory[addr+1] = u8((u16(imm.value) & 0xFF00) >> 8)
-                } else {
-                    cpu.memory[addr] = u8(imm.value)
-                }
-            }
-        }
-    } else if mem_addr,ok := inst.dst.(MemoryAddr); ok {
-        #partial switch inst.opname {
-        case .MOV:
-            value := get_operand_value(cpu, inst.src)
-
-            effective_addr_val := get_effective_address_value(cpu, mem_addr.addr_id)
-            addr := effective_addr_val + mem_addr.displacement_value
-            cpu.memory[addr]   = u8(value & 0x00FF)
-            cpu.memory[addr+1] = u8((u16(value) & 0xFF00) >> 8)
-
-            // TODO: We need a way to detect if it's a byte or a word
-            // if imm,ok := inst.src.(Immediate); ok {
-            //     // TODO: We need a function that returns the registers to check out
-            //     effective_addr_val := get_effective_address_value(cpu, mem_addr.addr_id)
-            //     addr := effective_addr_val + mem_addr.displacement_value
-            //     if imm.size == .Signed16 {
-            //         cpu.memory[addr]   = u8(imm.value & 0x00FF)
-            //         cpu.memory[addr+1] = u8((u16(imm.value) & 0xFF00) >> 8)
-            //     } else {
-            //         cpu.memory[addr] = u8(imm.value)
-            //     }
-            // }
-        }
-    } else if jmp_offset,ok := inst.src.(Jump); ok {
         jump: bool
         #partial switch inst.opname {
         case .JNZ, .JNE: jump = !cpu.flags[.ZF]
@@ -175,6 +111,9 @@ execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
         case .JP, .JPE:  jump =  cpu.flags[.PF]
         case .JB, .JNAE: jump =  cpu.flags[.CF]
 
+        case .LOOP:
+            cpu.registers[.cx].full -= 1
+            jump = cpu.registers[.cx].full != 0
         case .LOOPNZ, .LOOPNE:
             cpu.registers[.cx].full -= 1
             // According to this resource, the loopnz inst does not change any flags
@@ -186,6 +125,30 @@ execute_instruction :: proc(cpu: ^Cpu, inst: Instruction) {
             cpu.registers[.ip].full += i16(jmp_offset)
             cpu.registers[.ip].full -= i16(inst.bytes_read)
         }
+        return
+    }
+    status_flags := bit_set[Flag]{.OF, .SF, .ZF, .AF, .PF, .CF}
+    #partial switch inst.opname {
+    case .MOV:
+        src_val := perform_load(cpu, inst.src, inst.is_word)
+        perform_store(cpu, src_val, inst.dst, inst.is_word)
+    case .ADD:
+        src_val := perform_load(cpu, inst.src, inst.is_word)
+        dst_val := perform_load(cpu, inst.dst, inst.is_word)
+        val := dst_val + src_val
+        perform_store(cpu, val, inst.dst, inst.is_word)
+        check_flags(cpu, status_flags, dst_val, src_val, val, true)
+    case .SUB:
+        src_val := perform_load(cpu, inst.src, inst.is_word)
+        dst_val := perform_load(cpu, inst.dst, inst.is_word)
+        val := dst_val - src_val
+        perform_store(cpu, val, inst.dst, inst.is_word)
+        check_flags(cpu, status_flags, dst_val, src_val, val, false)
+    case .CMP:
+        src_val := perform_load(cpu, inst.src, inst.is_word)
+        dst_val := perform_load(cpu, inst.dst, inst.is_word)
+        val := dst_val - src_val
+        check_flags(cpu, status_flags, dst_val, src_val, val, false)
     }
 }
 

instructions.odin

@@ -194,16 +194,13 @@ instructions := [?]InstructionInfo {
       dst = .Accumulator, src = .Register,
       reg_info = .FirstByteLast3, has_flip = true, word_size = .Always16 },
     { opname = .IN, desc = "", mask = 0b11111110, encoding = 0b11100100,
-      dst = .Accumulator, src = .ImmediateUnsigned },
+      dst = .Accumulator, src = .Immediate, word_size = .LastBit },
     { opname = .IN, desc = "", mask = 0b11111110, encoding = 0b11101100,
-      dst = .Accumulator, src = .VariablePort,
+      dst = .Accumulator, src = .VariablePort, word_size = .LastBit, },
-      word_size = .LastBit, },
     { opname = .OUT, desc = "", mask = 0b11111110, encoding = 0b11100110,
-      dst = .ImmediateUnsigned, src = .Accumulator,
+      dst = .VariablePort, src = .Accumulator, word_size = .LastBit },
-      word_size = .LastBit, },
     { opname = .OUT, desc = "", mask = 0b11111110, encoding = 0b11101110,
-      dst = .VariablePort, src = .Accumulator,
+      dst = .VariablePort, src = .Accumulator, word_size = .LastBit, },
-      word_size = .LastBit, },
     { opname = .TEST, desc = "", mask = 0b11111110, encoding = 0b10101000,
       dst = .Accumulator, src = .Immediate, word_size = .LastBit },
     { opname = .XLAT, desc = "", mask = 0b11111111, encoding = 0b11010111,},

printing.odin

@@ -39,7 +39,7 @@ calculate_effective_address :: proc(r_m: u8) -> string {
 
 get_memory_string :: proc(memoryAddr: MemoryAddr, has_segment: Maybe(RegisterId)) -> string {
     disp: string
-    value := memoryAddr.displacement_value
+    value := memoryAddr.displacement
     if value != 0 {
         disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
     }
@@ -70,14 +70,7 @@ get_operand_string :: proc(operand: Operand, has_segment: Maybe(RegisterId)) ->
     case RegisterId:
         string_val = get_register_name(val)
     case Immediate:
-        switch val.size {
+        string_val = fmt.aprintf("%d", val.value)
-        case .Signed8:
-            string_val = fmt.aprintf("%d", i8(val.value))
-        case .Unsigned8:
-            string_val = fmt.aprintf("%d", u8(val.value))
-        case .Signed16:
-            string_val = fmt.aprintf("%d", i16(val.value))
-        }
     case MemoryAddr:
         string_val = get_memory_string(val, has_segment)
     case DirectAddress:
@@ -131,15 +124,9 @@ get_instruction_string :: proc(inst_info: InstructionInfo, instruction: Instruct
             interseg_string = " far"
         }
         fmt.sbprintf(&instruction_builder, "%s%s %s%s", opname, interseg_string, size_string, src_str)
-    } else {
-        // note: i don't know why this is the case, but only the move has the word/byte
-        // keyword next to the immediate, but other instructions have it on the memory address
-        if opname == "mov" {
-            fmt.sbprintf(&instruction_builder, "%s %s, %s%s", opname, dst_str, size_string, src_str)
     } else {
         fmt.sbprintf(&instruction_builder, "%s %s%s, %s", opname, size_string, dst_str, src_str)
     }
-    }
 
     // Prepare padding and comment to add debug info
     b_len := strings.builder_len(instruction_builder)

sim8086.odin

@@ -6,6 +6,7 @@ import "core:fmt"
 import "core:math"
 import "core:strings"
 import "core:reflect"
+import "core:strconv"
 
 main :: proc() {
     f,err := os.open(os.args[1])
@@ -47,7 +48,12 @@ main :: proc() {
         memory = make([dynamic]u8, 1024 * 1024), // 1,048,576
     }
 
+    num_idx := strings.last_index(os.args[1], "list-") + 5
+    if listing_num,ok := strconv.parse_int(os.args[1][num_idx:num_idx+4]); ok {
+        if listing_num > 42 {
             execute_instructions(&cpu, decoded_insts)
+        }
+    }
 
     if what_to_print == "registers" || what_to_print == "all" {
         fmt.println("Registers")
@@ -66,8 +72,9 @@ main :: proc() {
 
         failed_ref: bool
         path,ok := strings.replace(os.args[1], ".bin", ".txt", 1)
-        ref_cpu,_ := extract_reference_cpu_state(path)
+        ref_cpu,_ := parse_reference_cpu_state(path)
         for reg_val,name in ref_cpu.registers {
+            if name == .ip && reg_val.full == 0 do continue
             if cpu.registers[name].full != reg_val.full {
                 msg := "%s register does not match reference - Expected 0x%04x | Actual 0x%04x"
                 fmt.printfln(msg, name, reg_val.full, cpu.registers[name].full)
@@ -88,4 +95,18 @@ main :: proc() {
     if what_to_print == "instructions" || what_to_print == "all" {
         print_instructions_stdout(instructions_list[:])
     }
+    if len(os.args) > 3 && os.args[3] == "dump" {
+        f2,open_err := os.open("./listing-54.data", os.O_WRONLY|os.O_CREATE|os.O_TRUNC, 0o644)
+        if open_err == nil {
+            bytes_written,write_err := os.write(f2, cpu.memory[:])
+            if write_err == nil {
+                fmt.println("Dumpped", bytes_written, "to disk: listing-54.data")
+            } else {
+                fmt.println("Error2:", write_err)
+            }
+        } else {
+            fmt.println("Error1:", open_err)
+        }
+        defer os.close(f)
+    }
 }

testing.odin

@@ -7,7 +7,12 @@ import "core:strings"
 import "core:strconv"
 import "core:reflect"
 
-extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
+get_cpu_register_by_name :: proc(cpu: ^Cpu, name: string) -> ^RegisterValue {
+    reg,_ := reflect.enum_from_name(Register, name)
+    return &cpu.registers[reg]
+}
+
+parse_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
     cpu: Cpu
 
     data,ok := os.read_entire_file(filename)
@@ -20,7 +25,6 @@ extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
     lines := strings.split(content, "\n")
     defer delete(lines)
 
-    ignore_ip_reg := true
     for line in lines {
         space_count := 0
         for c,i in line {
@@ -42,9 +46,6 @@ extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
                     }
                 } else {
                     reg_name := line[i:i+2]
-                    if reg_name == "ip" {
-                        ignore_ip_reg = false
-                    }
                     reg_value := get_cpu_register_by_name(&cpu, reg_name)
                     hex_string := line[i+6:i+10]
                     if hex_num,ok := strconv.parse_int(hex_string, 16); ok {
@@ -56,9 +57,5 @@ extract_reference_cpu_state :: proc(filename: string) -> (Cpu, bool) {
         }
     }
 
-    if ignore_ip_reg {
-        cpu.registers[.ip] = cpu.registers[.ip]
-    }
-
     return cpu, true
 }

types.odin

@@ -58,9 +58,8 @@ RegisterId :: struct {
     access: RegisterAccess,
 }
 ImmediateSize :: enum {
-    Signed8,
+    _8,
-    Unsigned8,
+    _16,
-    Signed16,
 }
 Immediate :: struct {
     value: i16,
@@ -68,8 +67,8 @@ Immediate :: struct {
 }
 MemoryAddr :: struct {
     addr_id: u8,
-    displacement_value: i16,
+    displacement: i16,
-    displacement_size: ImmediateSize,
+    disp_size: ImmediateSize,
 }
 DirectAddress :: distinct i16
 Jump :: distinct i8
@@ -96,7 +95,6 @@ OperandInfo :: enum {
     SegmentRegister,
     RegisterMemory,
     Immediate,
-    ImmediateUnsigned,
     Accumulator,
     DirectAddress,
     Jump,
@@ -122,6 +120,7 @@ InstructionInfo :: struct {
     desc: string,
     src: OperandInfo,
     dst: OperandInfo,
+    flags: bit_set[Flag],
     word_size: WordSize,
     reg_info: RegisterEncodingBits,
     has_flip: bool,