97 lines
3.2 KiB
Org Mode
97 lines
3.2 KiB
Org Mode
#+OPTIONS: toc:nil
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* 8086 CPU Simulator
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A complete 8086 processor emulator written in Odin, featuring instruction decoding, execution, and cycle-accurate simulation. Implements a comprehensive subset of the Intel 8086 instruction set with proper flag handling, memory management, and register operations.
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** Features
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- *Complete 8086 instruction decoding* - Supports MOV, arithmetic, jumps, loops, stack operations, and more
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- *Cycle-accurate execution* - Proper CPU state management with registers and flags
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- *Memory simulation* - 1MB addressable memory space with effective address calculation
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- *Comprehensive testing* - 21 assembly test programs with automated validation
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- *Reference validation* - Compares execution results against reference CPU states
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** Architecture
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The simulator is organized into several focused modules:
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- =sim8086.odin= - Main entry point and program orchestration
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- =types.odin= - Core data structures (CPU state, instructions, operands)
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- =instructions.odin= - Complete 8086 instruction set definitions
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- =decoding.odin= - Binary instruction decoding and parsing
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- =execution.odin= - CPU execution engine with flag calculations
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- =printing.odin= - Assembly output formatting
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- =testing.odin= - Reference state parsing and validation
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** Building and Running
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#+BEGIN_SRC bash
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# Build the simulator
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make
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# Decode and print assembly
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./sim8086 program.bin instructions
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# Execute with register dump
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./sim8086 program.bin registers
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# Full execution with memory dump
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./sim8086 program.bin all dump
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#+END_SRC
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** Testing
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Comprehensive test coverage included:
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#+BEGIN_SRC bash
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# Run all assembly tests
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./test_asm.sh
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# Run reference CPU validation tests
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./test_ref_cpu.sh
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#+END_SRC
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Test files cover:
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- Basic MOV operations and addressing modes
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- Arithmetic and logical operations with proper flag setting
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- Jump and loop instructions
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- Stack operations (PUSH/POP)
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- Complex programs with multiple instruction types
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** Technical Implementation
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*** Instruction Decoding
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- Bit-level parsing of 8086 machine code
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- Support for all addressing modes (register, immediate, memory, direct)
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- Proper handling of prefixes and multi-byte instructions
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*** Execution Engine
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- Register file with proper 8/16-bit access patterns
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- CPU flags (Zero, Carry, Sign, Overflow, etc.) with accurate calculations
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- Effective address computation for memory operations
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- Instruction pointer management and control flow
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*** Memory Model
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- 1MB linear address space
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- Little-endian byte ordering
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- Memory-mapped I/O simulation
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** Supported Instructions
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*Data Movement:* MOV, PUSH, POP, XCHG, LEA, LDS, LES
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*Arithmetic:* ADD, SUB, MUL, DIV, INC, DEC, CMP, NEG
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*Logical:* AND, OR, XOR, NOT, TEST
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*Shifts/Rotates:* SHL, SHR, SAR, ROL, ROR, RCL, RCR
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*Control Flow:* JMP, JE, JNE, JL, JG, LOOP, CALL, RET
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*String Operations:* MOVS, CMPS, SCAS, LODS, STOS
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*System:* INT, IRET, HLT, NOP
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Built following the [[https://www.computerenhance.com/p/table-of-contents][Performance Aware Programming]] course by Casey Muratori.
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** License
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This project is licensed under the MIT License - see the LICENSE file for details.
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*Note:* Some test files are derived from the Performance Aware Programming course materials. Consider supporting the course if you find this project useful.
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