374 lines
10 KiB
Odin
374 lines
10 KiB
Odin
package decoder_8086
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import "core:os"
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import "core:fmt"
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import "core:math"
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Register :: struct {
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fullname: string,
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bytename: string,
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value: struct #raw_union {
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using _: struct {
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low, high: byte,
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},
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full: u16,
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},
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code: u8,
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}
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OpName :: enum {
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MOV,
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ADD,
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SUB,
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CMP,
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JMP,
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}
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registers := [8]Register {
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{fullname = "ax", bytename = "al", code = 0b000},
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{fullname = "cx", bytename = "cl", code = 0b001},
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{fullname = "dx", bytename = "dl", code = 0b010},
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{fullname = "bx", bytename = "bl", code = 0b011},
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{fullname = "sp", bytename = "ah", code = 0b100},
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{fullname = "bp", bytename = "ch", code = 0b101},
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{fullname = "si", bytename = "dh", code = 0b110},
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{fullname = "di", bytename = "bh", code = 0b111},
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}
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RegInfo :: struct {
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in_first_byte: bool,
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shift_offset: u8,
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}
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LastBit :: struct{}
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FourthBit :: struct{}
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WordSize :: union {
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None,
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LastBit,
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FourthBit,
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}
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InstructionInfo :: struct {
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mask: u8,
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encoding: u8,
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name: string,
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desc: string,
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has_mod_rm: bool,
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word_size: WordSize,
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reg_info: Maybe(RegInfo),
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has_data: bool,
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has_displacement: bool,
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has_segreg: bool,
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has_flip: bool,
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has_explicit_size: bool,
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has_accumulator: bool,
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}
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reg_first_last := RegInfo{ in_first_byte = true, shift_offset = 0 }
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reg_second_middle := RegInfo{ in_first_byte = false, shift_offset = 3 }
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instructions := [?]InstructionInfo {
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{ name = "mov", desc = "Register/memory to/from register", mask = 0b11111100, encoding = 0b10001000,
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has_mod_rm = true, reg_info = reg_second_middle, has_data = false, has_displacement = true,
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word_size = LastBit{}, has_flip = true },
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{ name = "mov", desc = "Immediate to register/memory", mask = 0b11111110, encoding = 0b11000110,
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has_mod_rm = true, reg_info = nil, has_data = true, has_displacement = true,
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word_size = LastBit{}, has_explicit_size = true },
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{ name = "mov", desc = "Immediate to register", mask = 0b11110000, encoding = 0b10110000,
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has_mod_rm = false, reg_info = reg_first_last, has_data = true, has_displacement = false,
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word_size = FourthBit{} },
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{ name = "mov", desc = "Memory to accumulator", mask = 0b11111110, encoding = 0b10100000,
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has_mod_rm = false, reg_info = nil, has_data = true, has_displacement = false, has_flip = true,
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word_size = LastBit{}, has_accumulator = true },
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{ name = "mov", desc = "Accumulator to memory", mask = 0b11111110, encoding = 0b10100010,
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has_mod_rm = false, reg_info = nil, has_data = true, has_displacement = false, has_flip = true,
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word_size = LastBit{}, has_accumulator = true },
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{ name = "mov", desc = "Register/memory to segment register", mask = 0b11111111, encoding = 0b10001110,
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has_mod_rm = true, reg_info = nil, has_segreg = true, has_displacement = true,
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word_size = None{} },
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{ name = "mov", desc = "Segment register to register/memory", mask = 0b11111111, encoding = 0b10001100,
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has_mod_rm = true, reg_info = nil, has_segreg = true, has_displacement = true,
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word_size = None{} },
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}
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None :: struct {}
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Disp8 :: i8
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Disp16 :: i16
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Displacement :: union {
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None,
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Disp8,
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Disp16
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}
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Value8 :: i8
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Value16 :: i16
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Data :: union {
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None,
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Value8,
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Value16
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}
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ModMemory :: struct {}
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Mod8BitDisp :: i8
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Mod16BitDisp :: i16
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ModRegister :: struct {}
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ModMode :: union {
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ModMemory,
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Mod8BitDisp,
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Mod16BitDisp,
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ModRegister,
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}
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RegisterId :: distinct u8
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Immediate8 :: distinct i8
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Immediate16 :: distinct i16
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MemoryAddr :: struct {
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addr_id: u8,
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displacement: Displacement
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}
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DirectAddress :: distinct i16
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Accumulator8 :: distinct i8
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Accumulator16 :: distinct i16
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OperandType :: union {
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RegisterId,
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Immediate8,
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Immediate16,
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MemoryAddr,
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DirectAddress,
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Accumulator8,
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Accumulator16,
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}
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inst_map := make(map[u8]InstructionInfo)
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RIGHT_ALIGN_AMOUNT := 30
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calculate_effective_address :: proc(r_m: u8) -> string {
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val: string
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switch r_m {
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case 0b000:
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val = "bx + si"
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case 0b001:
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val = "bx + di"
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case 0b010:
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val = "bp + si"
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case 0b011:
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val = "bp + di"
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case 0b100:
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val = "si"
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case 0b101:
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val = "di"
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case 0b110:
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val = "bp"
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case 0b111:
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val = "bx"
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}
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return val
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}
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get_memory_string :: proc(memoryAddr: MemoryAddr) -> string {
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disp: string
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switch value in memoryAddr.displacement {
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case None:
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disp = ""
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case Disp8:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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case Disp16:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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}
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text := fmt.aprintf("[%s%s]", calculate_effective_address(memoryAddr.addr_id), disp)
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return text
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}
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get_memory_type_string :: proc(mem_type: OperandType, is_word: bool) -> string {
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switch val in mem_type {
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case RegisterId:
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return is_word ? registers[val].fullname : registers[val].bytename
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case Immediate8:
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return fmt.aprintf("%d", val)
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case Immediate16:
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return fmt.aprintf("%d", val)
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case MemoryAddr:
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return get_memory_string(val)
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case DirectAddress:
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return fmt.aprintf("[%d]", val)
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case Accumulator8:
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return fmt.aprintf("[%d]", val)
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case Accumulator16:
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return fmt.aprintf("[%d]", val)
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}
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return ""
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}
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get_i16 :: proc(data: []u8) -> i16 {
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return (i16)(data[1]) << 8 | (i16)(data[0])
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}
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parse_displacement :: proc(data: []u8) -> (displacement: Displacement, disp_amount: int) {
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mod := (data[0] & 0b11000000) >> 6
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disp: Displacement = None{}
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amount: int
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switch mod {
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case 1:
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disp = (i8)(data[1])
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amount = 1
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case 2:
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disp = get_i16(data[1:])
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amount = 2
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}
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return disp, amount
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}
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get_displacement_string :: proc(displacement: Displacement) -> string {
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disp := ""
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#partial switch value in displacement {
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case i8:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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case i16:
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if value != 0 {
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disp = fmt.aprintf(" %s %d", value > 0 ? "+" : "-", math.abs(value))
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}
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}
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return disp
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}
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try_find_instruction :: proc(b: u8) -> (InstructionInfo, bool) {
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mask: u8 = 0xFF
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for j in 0..=4 {
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encoding := b & mask
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if inst, ok := inst_map[encoding]; ok {
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return inst, true
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}
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mask <<= 1
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}
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return InstructionInfo{}, false
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}
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main :: proc() {
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f,err := os.open(len(os.args) > 1 ? os.args[1] : "./asm_files/01-02-39.bin")
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// f,err := os.open(len(os.args) > 1 ? os.args[1] : "./asm_files/01-02-40.bin")
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if err != os.ERROR_NONE {
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os.exit(1)
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}
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defer os.close(f)
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data := make([]u8, 512)
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bytes_read, err2 := os.read(f, data)
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if err2 != nil {
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// ...
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os.exit(1)
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}
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for inst in instructions {
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inst_map[inst.encoding] = inst
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}
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if false {
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os.exit(0)
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}
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// asdf :u16 = 0b1111_0000_1001_0100
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// asdf2 :i16 = (i16)(asdf)
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// fmt.printfln("%d", asdf2)
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read_next := false
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src_dst := true
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fmt.println("bits 16\n")
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idx := 0
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for idx < bytes_read {
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processed := 1
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curr_byte := data[idx]
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instruction, ok := try_find_instruction(curr_byte)
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if !ok {
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txt := "unknown instruction"
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fmt.printfln("%s %*[1]s %8b", txt, RIGHT_ALIGN_AMOUNT - len(txt), ";;", curr_byte)
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idx += 1
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continue
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}
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lhs2: OperandType
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rhs2: OperandType
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is_word: bool
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is_immediate := false
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flip_dst := false
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rm: u8
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mod: u8
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reg: u8
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if instruction.has_flip {
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flip_dst = curr_byte & 2 != 0
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}
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switch val in instruction.word_size {
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case LastBit: is_word = curr_byte & 1 == 1
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case FourthBit: is_word = curr_byte & 0b0000_1000 != 0
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case None:
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}
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if reg_info, ok := instruction.reg_info.(RegInfo); ok {
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b := reg_info.in_first_byte ? data[idx] : data[idx+1]
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reg = (b >> reg_info.shift_offset) & 0b111
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}
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if instruction.has_mod_rm {
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mod = data[idx+1] >> 6
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rm = data[idx+1] & 0b00000111
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processed += 1 + ((int)(mod) % 3)
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if mod == 0 {
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if rm == 0b110 {
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lhs2 = (DirectAddress)(get_i16(data[idx+2:]))
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processed += 2
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} else {
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lhs2 = MemoryAddr{ addr_id = rm , displacement = None{} }
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}
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} else if mod == 1 {
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lhs2 = MemoryAddr{ addr_id = rm , displacement = (i8)(data[idx+2]) }
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} else if mod == 2 {
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lhs2 = MemoryAddr{ addr_id = rm , displacement = get_i16(data[idx+2:]) }
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} else if mod == 3 {
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lhs2 = (RegisterId)(registers[rm].code)
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}
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if instruction.has_explicit_size {
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imm_idx := idx + 2 + ((int)(mod) % 3)
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rhs2 = (OperandType)(is_word ? (Immediate16)(get_i16(data[imm_idx:])) : (Immediate8)(data[imm_idx]))
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processed += is_word ? 2 : 1
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} else {
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rhs2 = (RegisterId)(reg)
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}
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} else {
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lhs2 = (RegisterId)(registers[reg].code)
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if instruction.has_accumulator {
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rhs2 = (OperandType)(is_word ? ((Accumulator16)(get_i16(data[idx+1:]))) : ((Accumulator8)(data[idx+1])))
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} else {
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rhs2 = (OperandType)(is_word ? ((Immediate16)(get_i16(data[idx+1:]))) : ((Immediate8)(data[idx+1])))
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}
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processed += is_word ? 2 : 1
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}
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if flip_dst {
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lhs2, rhs2 = rhs2, lhs2
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}
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lhs := get_memory_type_string(lhs2, is_word)
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rhs := get_memory_type_string(rhs2, is_word)
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size_string := instruction.has_explicit_size ? is_word ? "word " : "byte " : ""
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full_inst := fmt.aprintf("%s %s, %s%s", instruction.name, lhs, size_string, rhs)
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fmt.printf("%s %*[1]s a", full_inst, RIGHT_ALIGN_AMOUNT - len(full_inst), ";;")
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for i in 0..<processed {
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fmt.printf(" %08b", data[idx + i])
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}
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fmt.println()
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idx += processed
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}
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}
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