60 lines
2.4 KiB
Odin
60 lines
2.4 KiB
Odin
package sim_8086
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import "core:os"
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import "core:fmt"
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import "core:math"
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import "core:strings"
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execute_instruction :: proc(inst: Instruction) {
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#partial switch inst.opname {
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case .MOV:
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if reg_id,ok := inst.dst.(RegisterId); ok {
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// val := registers[reg_id.id].value.full
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#partial switch val in inst.src {
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case Immediate8:
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if reg_id.access == .Low {
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registers[reg_id.id].value.low = (u8)(val)
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} else {
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registers[reg_id.id].value.high = (u8)(val)
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}
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case ImmediateU8:
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if reg_id.access == .Low {
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registers[reg_id.id].value.low = (u8)(val)
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} else {
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registers[reg_id.id].value.high = (u8)(val)
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}
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case Immediate16:
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registers[reg_id.id].value.full = (u16)(val)
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case RegisterId:
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switch val.access {
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case .Low, .High:
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value := val.access == .Low ? registers[val.id].value.low : registers[val.id].value.high
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if reg_id.access == .Low {
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registers[reg_id.id].value.low = value
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} else {
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registers[reg_id.id].value.high = value
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}
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case .Full:
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registers[reg_id.id].value.full = registers[val.id].value.full
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}
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case SegmentRegister:
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registers[reg_id.id].value.full = segment_registers[val].value.full
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}
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// fmt.printfln("%s:%04x->%04x", registers[reg_id].fullname, val, registers[reg_id].value.full)
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} else if reg_id,ok := inst.dst.(SegmentRegister); ok {
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// val := segment_registers[reg_id].value.full
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#partial switch val in inst.src {
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case Immediate8:
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segment_registers[reg_id].value.low = (u8)(val)
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case ImmediateU8:
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segment_registers[reg_id].value.low = (u8)(val)
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case Immediate16:
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segment_registers[reg_id].value.full = (u16)(val)
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case RegisterId:
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segment_registers[reg_id].value.full = registers[val.id].value.full
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}
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// fmt.printfln("%s:%04x->%04x", segment_registers[reg_id].fullname, val, segment_registers[reg_id].value.full)
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}
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}
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}
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