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11 Commits

Author SHA1 Message Date
Joseph Ferano
11ccfe78a9 Handle Memory movs, change displacement from union to enum 2025-03-21 20:11:39 +07:00
Joseph Ferano
99fd7fabd7 Add inst decoded type for better modeling, handle jumps correctly with IP register 2025-03-21 16:33:58 +07:00
Joseph Ferano
731e5bd45d CF, OF, and PF flags, keep values as i16, update ref test script 2025-03-20 20:22:12 +07:00
Joseph Ferano
5cf4768b80 Decode then check reference flags, change registers and flags to use enumerated arrays 2025-03-20 16:13:37 +07:00
Joseph Ferano
08874c4533 Use an enum to represent registers, parse txt files, check CPU state against expected 2025-03-20 13:06:33 +07:00
Joseph Ferano
305ac557fa Move registers to CPU struct, start working on testing code 2025-03-20 09:44:41 +07:00
Joseph Ferano
b511c6a620 Clean up/inline functions and clear out TODOs 2025-03-20 08:19:20 +07:00
Joseph Ferano
863ccfc583 Convert TBD instruction op names to the actual enum variants, rather than strings 2025-03-19 21:09:42 +07:00
Joseph Ferano
a91c3d9ba9 Clean up operand code by removing unnecessary variants 2025-03-19 18:57:34 +07:00
Joseph Ferano
c312b7fd57 Fix register logic since we can access high and low parts, it's really ugly 2025-03-18 21:16:08 +07:00
Joseph Ferano
32ddb518e9 Break code up into files, delete C code, organize things better 2025-03-15 17:28:51 +07:00
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