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• 85a8172923 Add .LOOP instruction, dump memory to disk with cli arg master Joseph Ferano 2025-03-23 08:58:29 +07:00
• fafb440891 Listings 54 and 55 Joseph Ferano 2025-03-23 08:58:12 +07:00
• df105ea3cf Generalize with perform_load and perform_store, use bit_set for cpu flags Joseph Ferano 2025-03-22 18:54:36 +07:00
• 831a307975 Fix and simplify (delete) all the signage stuff Joseph Ferano 2025-03-22 15:21:47 +07:00
• ea7b65994b Fix IN and OUT instructions decoding Joseph Ferano 2025-03-22 15:20:48 +07:00
• ab2b107e7e Listing 53 Joseph Ferano 2025-03-22 15:09:00 +07:00
• da78d875c1 Effective address movs work, but at what cost? Joseph Ferano 2025-03-21 20:47:42 +07:00
• 3ca4059c44 Listing 52 Joseph Ferano 2025-03-21 20:47:34 +07:00
• 11ccfe78a9 Handle Memory movs, change displacement from union to enum Joseph Ferano 2025-03-21 20:11:39 +07:00
• 948960e8f5 Listing 51 Joseph Ferano 2025-03-21 20:11:20 +07:00
• 0e90e2c23c Handle additional jumps for listing 50 Joseph Ferano 2025-03-21 17:19:48 +07:00
• 99fd7fabd7 Add inst decoded type for better modeling, handle jumps correctly with IP register Joseph Ferano 2025-03-21 16:33:58 +07:00
• d0f91f15f8 Listings 48 and 49 Joseph Ferano 2025-03-21 16:33:24 +07:00
• 731e5bd45d CF, OF, and PF flags, keep values as i16, update ref test script Joseph Ferano 2025-03-20 20:22:12 +07:00
• 5cf4768b80 Decode then check reference flags, change registers and flags to use enumerated arrays Joseph Ferano 2025-03-20 16:13:37 +07:00
• cd5eada115 Listing 47 Joseph Ferano 2025-03-20 16:09:44 +07:00
• 08874c4533 Use an enum to represent registers, parse txt files, check CPU state against expected Joseph Ferano 2025-03-20 13:06:33 +07:00
• 305ac557fa Move registers to CPU struct, start working on testing code Joseph Ferano 2025-03-20 09:44:41 +07:00
• b511c6a620 Clean up/inline functions and clear out TODOs Joseph Ferano 2025-03-20 08:19:20 +07:00
• 266f7a7900 Factor out get/set actions to reduce duplication, execute add,sub,cmp and check flags Joseph Ferano 2025-03-19 21:10:22 +07:00
• 863ccfc583 Convert TBD instruction op names to the actual enum variants, rather than strings Joseph Ferano 2025-03-19 21:09:42 +07:00
• fd8f696627 Listing 46 Joseph Ferano 2025-03-19 21:07:11 +07:00
• a91c3d9ba9 Clean up operand code by removing unnecessary variants Joseph Ferano 2025-03-19 18:57:34 +07:00
• c312b7fd57 Fix register logic since we can access high and low parts, it's really ugly Joseph Ferano 2025-03-18 21:16:08 +07:00
• b78d043b6c Add new listings, supply cs register, fix segreg mov instruction Joseph Ferano 2025-03-17 21:51:52 +07:00
• 118ed482c1 Add listing 0044.txt, rm test files at the end of script Joseph Ferano 2025-03-16 23:55:26 +07:00
• 6e7783c623 Bash script to compare expected output, print values in a way that's easy to test Joseph Ferano 2025-03-16 23:45:37 +07:00
• 7e74d1e9a2 Print registers and execute basic mov instructions Joseph Ferano 2025-03-15 22:28:54 +07:00
• 32ddb518e9 Break code up into files, delete C code, organize things better Joseph Ferano 2025-03-15 17:28:51 +07:00
• 6909f75b35 Little bit more clean up Joseph Ferano 2025-03-13 21:59:37 +07:00
• d4216d793a Listing 43/44 asm files Joseph Ferano 2025-03-13 17:50:58 +07:00
• 3dca2254e1 Add helper proc to clean up the word/byte keyword Joseph Ferano 2025-03-13 17:50:32 +07:00
• 460e1a8700 Little bit of clean up and organization Joseph Ferano 2025-03-13 12:46:25 +07:00
• fc02debf65 Last bunch of instructions to get listing 42 fully read Joseph Ferano 2025-03-12 23:46:47 +07:00
• babb07cb43 Segment register for memory addresses and lock string Joseph Ferano 2025-03-12 11:31:14 +07:00
• 8967be44a0 Major refactor to define both operands so either can be empty Joseph Ferano 2025-03-12 11:07:40 +07:00
• 08ef7d901b IN, OUT, XLAT, LEA, LDS, LES, ADC Joseph Ferano 2025-03-07 19:27:01 +07:00
• 782ff93ace Handle accumulator differently, handle segment registers, handle unary, add instructions Joseph Ferano 2025-03-07 10:14:36 +07:00
• 390fedc848 Add more instructions, add segment registers, move types up, read more data Joseph Ferano 2025-03-07 10:13:49 +07:00
• c7ee622847 Rename listing files Joseph Ferano 2025-03-03 20:40:47 +07:00
• 6365bd73a0 Encode jump offsets, collect instruction lines as strings, print at end Joseph Ferano 2025-02-24 20:03:18 +07:00
• 1f9837b256 Change how we detect explicit word sizes, fix data_idx Joseph Ferano 2025-02-23 12:05:56 +07:00
• c1799fcac2 Jump instructions and read opname from 3-bit pattern Joseph Ferano 2025-02-22 22:03:14 +07:00
• 446848dffb Generalizing data and operand bracketing, to make add instrunction work Joseph Ferano 2025-02-21 23:35:24 +07:00
• bc0a8b65eb New declarative style instruction definition, generalized parsing Joseph Ferano 2025-02-21 21:53:11 +07:00
• f8f5744cd3 WIP: Separate parsing from printing, the easy way Joseph Ferano 2025-02-16 17:10:29 +07:00
• fbedf7cf67 Process mov instruction properly, 01-02-39.asm now decoded properly Joseph Ferano 2025-02-14 23:08:45 +07:00
• c5e9cfac44 Parse instruction function Joseph Ferano 2025-02-14 13:08:46 +07:00
• 7c48c5ed90 Debug print encoding map Joseph Ferano 2025-01-21 22:46:31 +07:00
• 444510cca2 RegMemMode enum, Instruction struct with 'mov' encodings, plus a map, read bytes Joseph Ferano 2025-01-21 22:45:49 +07:00
• 86428f0263 Test w flag and print with the bytes in comments Joseph Ferano 2025-01-21 14:50:30 +07:00
• f67f6de0b6 Update building and testing for new odin code Joseph Ferano 2025-01-21 14:50:03 +07:00
• 0e4aebff13 Odin port Joseph Ferano 2025-01-21 14:20:41 +07:00
• 021c4573fa ADD instruction sign extension bit handled and deleting old code Joseph Ferano 2024-01-17 00:51:55 +07:00
• 26c07aee61 Types and instruction specifications moved to decode.h Joseph Ferano 2024-01-16 21:46:41 +07:00
• a0ed11416e Instruction parser finished for MOV instructions with corner cases handled Joseph Ferano 2024-01-16 21:44:03 +07:00
• ca0742de3c WIP Refactor: Instruction parsing, decoding and printing split Joseph Ferano 2024-01-16 18:27:19 +07:00
• 8497316768 WIP Refactor: Instruction parser now works and basic decoding in place Joseph Ferano 2024-01-16 10:09:50 +07:00
• 4754a8cd4c WIP Refactor: Instruction parser using a struct Joseph Ferano 2024-01-15 22:52:58 +07:00
• 20d1aed742 mov_inst and add_inst procedures to avoid too much nesting Joseph Ferano 2024-01-15 20:16:01 +07:00
• 08753ea330 Immediate to register/memory conditionals condensed Joseph Ferano 2024-01-15 12:42:54 +07:00
• 5b2542b0dd Direct Address special case added(MOD 0 R/M 110) Joseph Ferano 2024-01-15 12:30:42 +07:00
• 2a92f04836 Bug: Cast to i16 was failing, casted unsigned char to sbyte before promoting Joseph Ferano 2024-01-15 11:59:51 +07:00
• f4d6835694 ASM test file improved error handling/reporting Joseph Ferano 2024-01-15 10:45:46 +07:00
• 094733ee70 MOV inst conditional branching cleaned up considerably, cause god it was ugly Joseph Ferano 2024-01-15 10:45:08 +07:00
• 7f094799e9 OPTION macro revamped with IF_LET_SOME Joseph Ferano 2024-01-15 08:07:17 +07:00
• 9f7e371a49 Part01-02: Immedate to register/memory wip, moved EAC from r/m map to function Joseph Ferano 2024-01-14 11:37:37 +07:00
• 9b1d8d4005 Bash script to test asm decoding output Joseph Ferano 2024-01-14 09:01:52 +07:00
• 3b6381f981 Part01-02: More mov instructions being handled Joseph Ferano 2024-01-13 22:18:26 +07:00
• 6066e930db Part01-01: Listing 38 with multiple mov instructions now working Joseph Ferano 2024-01-13 15:51:51 +07:00
• 6ad9f66bc7 Makefile compiles all asm files Joseph Ferano 2024-01-13 13:24:13 +07:00
• 285b54e95f Struct Register added to have a proper abstraction Joseph Ferano 2024-01-13 10:47:06 +07:00
• 3a803b5c23 License Joseph Ferano 2024-01-12 22:32:55 +07:00
• a0157a0759 Part01-01: Project setup and basic decoding Joseph Ferano 2024-01-12 22:20:51 +07:00